2018 76th Device Research Conference (DRC)最新文献

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Theory and Design of Electron Blocking Layers for III-N Based Laser Diodes by Numerical Simulation 基于数值模拟的III-N基激光二极管电子阻挡层理论与设计
2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442243
K. Mehta, Yuh-Shiuan Liu, Jialin Wang, Hoon Jeong, T. Detchprohm, Young Jae Park, S. Shen, R. Dupuis, P. Yoder
{"title":"Theory and Design of Electron Blocking Layers for III-N Based Laser Diodes by Numerical Simulation","authors":"K. Mehta, Yuh-Shiuan Liu, Jialin Wang, Hoon Jeong, T. Detchprohm, Young Jae Park, S. Shen, R. Dupuis, P. Yoder","doi":"10.1109/DRC.2018.8442243","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442243","url":null,"abstract":"Unlike laser diodes made of traditional III-V materials (III-AsP), III-Nitride laser diodes and LEDs suffer from reduced injection efficiency due to greater electron leakage [1]. The overflow of electrons out of the active region into the adjacent p-type quasi-neutral region (QNR) is primarily due to the asymmetry between majority carrier conductivities in p- and n-GaN [2], where the electron conductivity in n-GaN is more than 40 times greater than the hole conductivity in p-GaN [3], [4]. Furthermore, carrier leakage is exacerbated by interfacial spontaneous and piezoelectric polarization charges at III-N heterojunctions. To stem electron leakage, an electron blocking layer (EBL) is typically employed between the last quantum barrier (QB) and p-type quasi-neutral region (QNR), and this EBL is typically a thin layer of wide bandgap material.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117064801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
CMOS Technology with Integrated Carbon-Nanotube Contact Plugs 集成碳纳米管接触插头的CMOS技术
2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442155
C. Prawoto, Suwen Li, M. Chan
{"title":"CMOS Technology with Integrated Carbon-Nanotube Contact Plugs","authors":"C. Prawoto, Suwen Li, M. Chan","doi":"10.1109/DRC.2018.8442155","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442155","url":null,"abstract":"Although CMOS compatible CNT process in interconnect technology has been proposed [1], integration to a working active device has yet to be demonstrated. CNT synthesis in existing works employ the use of Ti-based substrate using Ni catalyst [2]. Nevertheless, the use of CNTs as MOSFET contact plugs in advanced technology node require the synthesis of CNTs on nickel silicided (NiSi) source and drain region [3]. Thus, in this paper, a CMOS compatible integration process of CNT contact plug to a MOSFET is proposed. The challenge of growing CNT from NiSi substrate is addressed using interfacial layer using Ni based catalyst. The performance of CNT vias integrated with a MOSFET is evaluated in terms of via resistance and IV characteristics.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121154105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Challenges and opportunities in integration of 2D materials on 3D substrates: Materials and device perspectives 在3D基板上集成2D材料的挑战和机遇:材料和器件的观点
2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442141
M. Neupane, D. Ruzmetov, R. Burke, A. G. Birdwell, Decarlos Taylor, M. Chin, T. O'Regan, F. Crowne, B. Nichols, P. Shah, E. Byrd, T. Ivanov
{"title":"Challenges and opportunities in integration of 2D materials on 3D substrates: Materials and device perspectives","authors":"M. Neupane, D. Ruzmetov, R. Burke, A. G. Birdwell, Decarlos Taylor, M. Chin, T. O'Regan, F. Crowne, B. Nichols, P. Shah, E. Byrd, T. Ivanov","doi":"10.1109/DRC.2018.8442141","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442141","url":null,"abstract":"In recent years, large investments into the research of semiconducting two-dimensional (2D) materials such as graphene and transition metal dichalcogenides (TMDs) have elucidated interesting device related physical phenomena such as valleytronics [1], 2D superconductivity [2], 2D excitonic effects [3] and vertical tunneling [4]. TMDs offer layer-dependent chemical tunability of electronic and optoelectronic properties governed by interlayer van der Waals (vdW) forces [5]. Because of their layered nature, these low-dimensional materials can be combined to form multifunctional heterostructure materials exhibiting entirely new physical systems offering new degrees of flexibility in designing electronics, optoelectronics and other novel devices [6], [7]. In the last couple of years, the focus in the 2D materials research have shifted from exploration of proof-of-concept devices using mechanically exfoliated materials to more advanced device processing using high-quality large-scale growth based on advanced scalable vdW-epitaxy techniques such as powder vapor deposition (PVD) and chemical vapor deposition (CVD).","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131184221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Approaches for Dynamic IR N ano-Optics using 2D Materials 基于二维材料的动态红外纳米光学方法
2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8444105
J. Caldwell
{"title":"Approaches for Dynamic IR N ano-Optics using 2D Materials","authors":"J. Caldwell","doi":"10.1109/DRC.2018.8444105","DOIUrl":"https://doi.org/10.1109/DRC.2018.8444105","url":null,"abstract":"The current state-of-the-art in materials used for IR optical components (e.g. focusing elements, waveplates or prisms) is far from ideal. This problem is exacerbated by the long free-space wavelengths associated with the mid-wave IR (MWIR) to terahertz (THz) spectral domains. Through the use of polaritons, one can surpass the diffraction limit and thus the limitations of these long free-space wavelengths can be circumvented. The two most prevalent varieties are the surface plasmon (SPP) and surface phonon polariton (SPhP), resulting from the coupling of light with electronic charges in a metal or ionic charges on a polar lattice, respectively. Each exhibits significant limitations, for instance the narrow, material specific operational “Reststrahlen band” of SPhPs and the relatively high optical losses in SPPs. Thus, it would be ideal to identify a method to dictate the IR/THz response, while retaining the positive attributes of both.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132447796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Bias Stress Stability of Carbon Nanotube Transistors with Implications for Sensors 碳纳米管晶体管的偏置应力稳定性及其对传感器的影响
2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442226
Steven G. Noyce, James L. Doherty, A. Franklin
{"title":"Bias Stress Stability of Carbon Nanotube Transistors with Implications for Sensors","authors":"Steven G. Noyce, James L. Doherty, A. Franklin","doi":"10.1109/DRC.2018.8442226","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442226","url":null,"abstract":"For years, carbon nanotube (CNT) field- effect transistors (CNTFETs) have been promoted for their superb performance in sensing applications [1]. As hollow cylinders of sp2-bonded carbon, CNTs have their entire crystal structure exposed and thus are highly sensitive to local charge perturbations. CNTFET -based sensors typically require constant biasing in the on-state for the duration of their operation, inducing both gate and drain bias stress in the device. Reliable sensors will require detailed understanding of the effects of this bias stress on the device performance; yet, reports of these effects to date have had limited focus, primarily studying gate bias stress [2]–[4], molecular adsorption [5], or exclusively CNT thin-film devices [2-3,7]. Additionally, these reports are limited to time scales of less than a few hours.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132492048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fast Recovery Performance of β-Ga2O3 Trench MOS Schottky Barrier Diodes β-Ga2O3沟槽MOS肖特基势垒二极管的快速恢复性能
2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442267
A. Takatsuka, K. Sasaki, D. Wakimoto, Q. Thieu, Y. Koishikawa, Junichi Arima, Jun Hirabayashi, Daisuke Inokuchi, Yoshiaki Fukumitsu, A. Kuramata, S. Yamakoshi
{"title":"Fast Recovery Performance of β-Ga2O3 Trench MOS Schottky Barrier Diodes","authors":"A. Takatsuka, K. Sasaki, D. Wakimoto, Q. Thieu, Y. Koishikawa, Junichi Arima, Jun Hirabayashi, Daisuke Inokuchi, Yoshiaki Fukumitsu, A. Kuramata, S. Yamakoshi","doi":"10.1109/DRC.2018.8442267","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442267","url":null,"abstract":"Gallium oxide (Ga<inf>2</inf>O<inf>3</inf>) is promising next-generation semiconductor material for high power and low loss devices. Its wide band gap of 4.5-4.9 eV results in a high breakdown field of <tex>$sim 8 mathrm{MV}/mathrm{cm}$</tex> and Baliga's FOM of <tex>$sim 3400$</tex>. Among several polytypes of Ga<inf>2</inf>O<inf>3</inf>, β-Ga<inf>2</inf>O<inf>3</inf> is the most viable option that can provide cost-effective and high-quality wafers with an edge-defined film-fed growth (EFG) method [1]. Several groups have reported excellent electric characteristics of vertical-type power devices using the β-Ga<inf>2</inf>O<inf>3</inf> wafers [2]–[4]. We also demonstrated Schottky barrier diodes (SBDs) [5], trench metal-oxide-semiconductor SBDs (MOSSBDs) [6], junction barrier Schottky diodes [7], and trench metal-oxide-semiconductor field-effect transistors (MOSFETs) [8].","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133251488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
The End of the Road for 2D Scaling of Silicon CMOS and the Future of Device Technology 硅CMOS二维缩放之路的终结与器件技术的未来
2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442185
H. Wong
{"title":"The End of the Road for 2D Scaling of Silicon CMOS and the Future of Device Technology","authors":"H. Wong","doi":"10.1109/DRC.2018.8442185","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442185","url":null,"abstract":"What will the semiconductor industry do after two-dimensional scaling of the silicon transistor crosses the nanometer threshold, from 7 nm, 5 nm, 3 nm, 2 nm, 1 nm, to nodes below a nanometer? Will these advanced logic technologies continue to provide the energy efficiency required of future computing systems? Will the transistor continue to play a key role in advancing electronic systems? Will new applications and computation workloads demand new device technologies and their integration into future systems? These are some of the most pressing questions facing the semiconductor industry today.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131362311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Nonlinearity Enhancement by Positive Pulse Stress in Multilevel Cell Selectorless RRAM Applications 多电平无选择器RRAM应用中正脉冲应力的非线性增强
2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442232
Ying‐Chen Chen, Xiaohan Wu, Yao‐Feng Chang, Jack C. Lee
{"title":"Nonlinearity Enhancement by Positive Pulse Stress in Multilevel Cell Selectorless RRAM Applications","authors":"Ying‐Chen Chen, Xiaohan Wu, Yao‐Feng Chang, Jack C. Lee","doi":"10.1109/DRC.2018.8442232","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442232","url":null,"abstract":"Resistive random access memory (RRAM) using various metal oxides (i.e., SiO2[1], HfO2, NiO[2], Al2O3, NbO) have attracted a great deal of attention since the current nonvolatile memory (NVM) has been approaching the scaling limits. Meanwhile, the undesired sneak current through neighboring unselected cells deteriorates the read margin and limits the maximum size of a crossbar array (i.e. read margin $sim$ 10%) [3]–[4]. And the selector devices have been used to resolve the sneak path current issue. However, the additional selector device in the so-called 1S-1R architecture (i.e. one selector-one resistor -Fig. 1 (a)) increases the cell size, process complexity, and cost. In this work, a nonlinear (NL) resistive switching (RS) in a multilevel lR-only selectorless RRAM cell has been demonstrated by using a graphite-based stacked RRAM device.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133875555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The Impact of Substrates on the Performance of Top-Gate p-Ga203 Field-Effect Transistors: Record High Drain Current of 980 mA/mm on Diamond 衬底对顶栅p-Ga203场效应晶体管性能的影响:在金刚石上记录980 mA/mm的高漏极电流
2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442276
J. Noh, M. Si, Hong Zhou, M. Tadjer, P. Ye
{"title":"The Impact of Substrates on the Performance of Top-Gate p-Ga203 Field-Effect Transistors: Record High Drain Current of 980 mA/mm on Diamond","authors":"J. Noh, M. Si, Hong Zhou, M. Tadjer, P. Ye","doi":"10.1109/DRC.2018.8442276","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442276","url":null,"abstract":"For high power devices, monolithic $beta$ -Ga203 has been identified as an emerging ultra-wide bandgap semiconductor material because it has a large bandgap of 4.8 eV and a high breakdown electric field of 8 MV/cm [1]. $beta$ -Ga203 has also the potential to realize low-cost large-size native bulk substrates by melt-grown methods [2], [3]. However, the output power density and the maximum drain current density of $beta$ -Ga203 devices can be seriously limited due to its low thermal conductivity $(kappa$ of 10–25 W/m·K and self-heating effect (SHE) [4], [5]. If the heat from the channel cannot be well dissipated through the substrate, SHE can lead to significant channel temperature increase, thus degrade the device performance and the long-term reliability [6]. In order to overcome this material constraint, we explored nano-membrane transferring technique and studied $beta$ -Ga203 nano-membrane field-effect transistors (FETs) on different foreign substrates such as sapphire $(kappa=40 mathrm{W}/mathrm{m}cdot mathrm{K})$ and Si02/Si $(kappa=1.5 mathrm{W}/mathrm{m}cdot text{K for} 270 text{nm SiO}_{2})$ and compared the impact of these substrates on the device performance [7]–[9]. In this work, furthermore, we demonstrate the first B-Ga203 Fet on a diamond substrate with an extremely high thermal conductivity of $1,000sim 2,200 mathrm{W}/mathrm{m}cdot mathrm{K}$ [10] and compare with devices on a sapphire or Si02/Si substrate.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130827143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Optical Gain and Loss Measurements of Semipolar III-nitride Laser Diodes with ITO/thin-p-GaN Cladding Layers ITO/薄p- gan包层半极性iii -氮化激光二极管的光学增益和损耗测量
2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442174
S. Mehari, D. Cohen, Daniel L. Becerrea, C. Weisbuch, S. Nakamura, S. Denbaars
{"title":"Optical Gain and Loss Measurements of Semipolar III-nitride Laser Diodes with ITO/thin-p-GaN Cladding Layers","authors":"S. Mehari, D. Cohen, Daniel L. Becerrea, C. Weisbuch, S. Nakamura, S. Denbaars","doi":"10.1109/DRC.2018.8442174","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442174","url":null,"abstract":"Laser diodes (LDs) based on the group III-nitride material system are forecasted to be the key components of next generation high-intensity white lighting systems [1]. For such systems, LDs offer more power per chip area, much higher spatial brightness, and no efficiency droop above threshold compared to light emitting diodes (LEDs). To meet these expectations, high-power and high-efficiency continuous-wave (CW) operation of a LD is essential. However, to date, InGaN LDs performance is still hampered by a high operating voltage and a poor differential efficiency, which result in lower wall-plug efficiencies (WPE) than InGaN LEDs or other III-V LDs [2], [3]. We have recently demonstrated an enhanced CW performance of blue LDs grown on a semipolar $(20bar{2}bar{1})$ n-GaN substrate by replacing part of the resistive p-GaN cladding layer with a tin-doped indium oxide (ITO) layer [4]. With this transparent conductive oxide (TCO) layer, which has a lower modal optical loss than standard metallic p-contacts, and thinned p-GaN layer a very low operating voltage was obtained. Here, we present detailed gain and absorption measurements of these devices. We show a very low optical loss by redesigning the AlGaN electron blocking layer and the p-waveguide doping profile.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134105954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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