Ying‐Chen Chen, Xiaohan Wu, Yao‐Feng Chang, Jack C. Lee
{"title":"多电平无选择器RRAM应用中正脉冲应力的非线性增强","authors":"Ying‐Chen Chen, Xiaohan Wu, Yao‐Feng Chang, Jack C. Lee","doi":"10.1109/DRC.2018.8442232","DOIUrl":null,"url":null,"abstract":"Resistive random access memory (RRAM) using various metal oxides (i.e., SiO2[1], HfO2, NiO[2], Al2O3, NbO) have attracted a great deal of attention since the current nonvolatile memory (NVM) has been approaching the scaling limits. Meanwhile, the undesired sneak current through neighboring unselected cells deteriorates the read margin and limits the maximum size of a crossbar array (i.e. read margin $\\sim$ 10%) [3]–[4]. And the selector devices have been used to resolve the sneak path current issue. However, the additional selector device in the so-called 1S-1R architecture (i.e. one selector-one resistor -Fig. 1 (a)) increases the cell size, process complexity, and cost. In this work, a nonlinear (NL) resistive switching (RS) in a multilevel lR-only selectorless RRAM cell has been demonstrated by using a graphite-based stacked RRAM device.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Nonlinearity Enhancement by Positive Pulse Stress in Multilevel Cell Selectorless RRAM Applications\",\"authors\":\"Ying‐Chen Chen, Xiaohan Wu, Yao‐Feng Chang, Jack C. Lee\",\"doi\":\"10.1109/DRC.2018.8442232\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Resistive random access memory (RRAM) using various metal oxides (i.e., SiO2[1], HfO2, NiO[2], Al2O3, NbO) have attracted a great deal of attention since the current nonvolatile memory (NVM) has been approaching the scaling limits. Meanwhile, the undesired sneak current through neighboring unselected cells deteriorates the read margin and limits the maximum size of a crossbar array (i.e. read margin $\\\\sim$ 10%) [3]–[4]. And the selector devices have been used to resolve the sneak path current issue. However, the additional selector device in the so-called 1S-1R architecture (i.e. one selector-one resistor -Fig. 1 (a)) increases the cell size, process complexity, and cost. In this work, a nonlinear (NL) resistive switching (RS) in a multilevel lR-only selectorless RRAM cell has been demonstrated by using a graphite-based stacked RRAM device.\",\"PeriodicalId\":269641,\"journal\":{\"name\":\"2018 76th Device Research Conference (DRC)\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 76th Device Research Conference (DRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DRC.2018.8442232\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 76th Device Research Conference (DRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2018.8442232","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Nonlinearity Enhancement by Positive Pulse Stress in Multilevel Cell Selectorless RRAM Applications
Resistive random access memory (RRAM) using various metal oxides (i.e., SiO2[1], HfO2, NiO[2], Al2O3, NbO) have attracted a great deal of attention since the current nonvolatile memory (NVM) has been approaching the scaling limits. Meanwhile, the undesired sneak current through neighboring unselected cells deteriorates the read margin and limits the maximum size of a crossbar array (i.e. read margin $\sim$ 10%) [3]–[4]. And the selector devices have been used to resolve the sneak path current issue. However, the additional selector device in the so-called 1S-1R architecture (i.e. one selector-one resistor -Fig. 1 (a)) increases the cell size, process complexity, and cost. In this work, a nonlinear (NL) resistive switching (RS) in a multilevel lR-only selectorless RRAM cell has been demonstrated by using a graphite-based stacked RRAM device.