2018 76th Device Research Conference (DRC)最新文献

{"title":"Steep-Slope Hysteresis-Free Negative-Capacitance 2D Transistors","authors":"P. Ye","doi":"10.1109/ICSICT.2018.8564814","DOIUrl":"https://doi.org/10.1109/ICSICT.2018.8564814","url":null,"abstract":"The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption [1]. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier [2]. Meanwhile, two-dimensional (2D) semiconductors, such as atomically thin transition metal dichalcogenides (TMDs) due to their low dielectric constant, and ease of integration in a junctionless transistor topology, offer enhanced electrostatic control of the channel. Here, we combine these two advantages and demonstrate for the first time a molybdenum disulfide (MOS2)2D steep slope transistor with a ferroelectric hafnium zirconium oxide layer (HZO) in the gate dielectric stack [3]. This device exhibits excellent performance in both on- and off-states, with maximum drain current of $510 mu mathrm{A}/mu mathrm{m}$, sub-thermionic subthreshold slope and is essentially hysteresis-free. Negative differential resistance (NDR) was observed at room temperature in the Mos2 negative capacitance field-effect-transistors (NC-FETs) as the result of negative capacitance due to the negative drain-induced-barrier-lowering (DIBL). High on-current induced self-heating effect was also observed and studied. We will also discuss the effect of internal metal gate [4], [5], p-type 2D transistors [6], and ferroelectric switch speed issues [7] in this talk. The work is in close collaborations with Mengwei Si, Wonil Chung, Chun-Jung Su, Chunsheng Jiang, Hong Zhou, Kerry D. Maize, Ali Shakouri, Muhammad A. Alam.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116874359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of hierarchical simulation framework for design and optimization of molecular based flash cell","authors":"V. Georgiev","doi":"10.1109/DRC.2018.8442234","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442234","url":null,"abstract":"The field of molecular electronics continues to spur interest in the quest for miniaturization and reduction of operational power of electron devices. Most of the systems described in the literature are based on organic molecules, such as benzene, ferrocene and fullerenes [1]. However, the use of inorganic molecules known as polyoxometalates (POMs) (see Fig. 1 and Fig. 2) could offer several important advantages over the conventional and organic based devices. The interest in POMs for flash cell applications stems from the fact that POMs are highly redox active molecules and that they can also be doped with electronically active heteroatoms [3]. They can undergo multiple reversible reductions/oxidations, which makes them attractive candidates for multi-bit storage in flash memory cells. Our recent work showed that POMs are more compatible with existing CMOS processes than organic molecules and they can replace the polysilicon floating gate in contemporary flash cell devices [2]. In this work, we discuss a further improvement and development of our simulation framework and models, e.g. Poisson distribution of the molecules in the oxide, introducing a various device geometry such as FDSOI and nanowires and improved simulation flow.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127863610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Energy-Efficient Phase Change Memory Programming by Nanosecond Pulses","authors":"E. Yalon, Kye L. Okabe, C. Neumann, H. Wong, E. Pop","doi":"10.1109/DRC.2018.8443164","DOIUrl":"https://doi.org/10.1109/DRC.2018.8443164","url":null,"abstract":"Phase change memory (PCM) is an important storage-class memory technology and a promising candidate for neuromorphic applications. PCM is based on the reversible resistance change in chalcogenide glasses, like Ge2Sb2Te5 (GST), which can be induced with Joule heating pulses. However, PCM often suffers from large programming energy during the reset (amorphization) process which requires heating the chalcogenide above its melting temperature $(T_{mathrm{m}}sim 600^{circ}mathrm{C})$. Recently, significant reductions in reset energy were achieved by scaling down cell dimensions thanks to the non-filamentary nature of PCM [1].","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116232018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-Performance Few-Layer Tellurium CMOS Devices Enabled by Atomic Layer Deposited Dielectric Doping Technique","authors":"G. Qiu, M. Si, Yixiu Wang, X. Lyu, Wenzhuo Wu, P. Ye","doi":"10.1109/DRC.2018.8442253","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442253","url":null,"abstract":"Tellurium (Te) is a p-type narrow bandgap (0.35 eV, direct) semiconductor with high hole mobility around 700 cm2/Vs. [1] The lattice of Te is formed by 1D helical atomic chains and the neighboring chains are interconnected by van der Waals forces as shown in Fig. 1(a) [2]. Recently a liquid-based synthesis method was proposed to produce high-quality large-area 2D tellurium films with atomic flat surfaces [1], and high-performance p-MOSFETs based on few-layer tellurium films were demonstrated with large on-state current ($(> 1$ A/mm), high on/off ratio (∼106) and great stability for over two months in air [1]. However, like most of other 2D materials, the lack of doping techniques [3], [4] to obtain its counterpart n-FETs is a major roadblock against the realization of Te CMOS or steep-slope devices. In this paper, for the first time, we demonstrated Te n-FETs enabled by atomic layer deposited (ALD) dielectric doping technique with large drive current (200 mA/mm) and reasonable on/off ratio (∼103). The n-FETs show almost symmetric operation as p-FETs and comparable field-effect mobility of 612 cm2/Vs. Using low work function metal, the on-state contact resistance is reduced to $4.3 mathrm{k}Omegacdotmu mathrm{m}$. The impacts of oxide layer type and thickness on doping effect are also systematically studied.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121847771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Improved 1T-DRAM Cell Using TiO2as the Source and Drain of an n-Channel PD-SOI MOSFET","authors":"Dibyendu Chatterjee, A. Kottantharayil","doi":"10.1109/DRC.2018.8442180","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442180","url":null,"abstract":"Due to fabrication challenges for the scaling of the capacitor of a conventional DRAM cell below 100 nm technology node, the concept of 1 T-DRAM cell[I] was proposed as an alternative. In all-Si 1T-DRAM cell, the body of an n-channel PD-SOI MOSFET is used as the storage node. The biggest drawback for all-Si 1 T-DRAM cell is it's low retention time which does not meet the ITRS specification (64 ms at 358 K) [2]. As a solution to this problem, we propose a novel capacitor-less 1 T-DRAM cell, where intrinsically n-type TiO2[3] is used as the sourceldrain material and silicon as the channel of an n-channel partially depleted SOI MOSFET. Large valance band offset between TiO2 and Si $(Delta E_{V}approx 2 eV)$ is utilized for storing larger number of excess holes in the body for a longer time than is possible with an all-Si 1T-DRAM cell. We report an improvement in retention time as well as sense margin at both $T=300 K$ and $T=358 K$ for our proposed DRAM cell through well calibrated TCAD simulations [4]. The extracted retention time for the proposed TiO2 source/drain 1T-DRAM cell is 3.5 s and 160 ms at $T=300 K$ and 358 $K$ respectively and for all-Si 1 T-DRAM cell, it is 1.5 ms and $150 mu s$ at $T=300 K$ and $T=358 K$ respectively.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114983027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Realization of the First GaN Based Tunnel Field-Effect Transistor","authors":"A. Chaney, H. Turski, K. Nomoto, Qingxiao Wang, Zongyang Hu, Moon J. Kim, H. Xing, D. Jena","doi":"10.1109/DRC.2018.8442249","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442249","url":null,"abstract":"Tunnel field-effect transistors (TFETs) offer the means to surpass the subthreshold swing (SS) limit of 60 mV/dec that limits MOSFETs. While MOSFETs rely on modulating a potential barrier, which is subject to a Boltzmann tail in the density of states (DOS), interband tunneling in TFETs enables a sharp turn off of the DOS because the transport is no longer governed by an exponential tail of carriers. These devices have been investigated in Si & III-V material systems1, achieving SS's as low as 20 mV/dec2. GaN is advantageous to these other material systems because its large bandgap is ideal for suppressing leakage current. Unfortunately impurity doping in GaN alone is not enough to achieve the internal fields required to promote interband tunneling[Fig l(a)]. However, by taking advantage of the difference in polarization fields between InGaN and GaN, a device structure favoring interband tunneling can be made [Fig l(b)]. Li et. al.3 have theoretically predicted that a GaN heterojunction TFET could obtain an SS of 15 mV/dec and a peak current of $1times 10^{-4} mathrm{A}/mu mathrm{m}$. For the work being presented, GaN TFETs were fabricated using a surrounding gate (SG) architecture utilizing both nanowires and fins formed from a top-down approach.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"84 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121016697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Ultra Energy Efficient Neuron enabled by Tunneling in Sub-threshold Regime on a Highly Manufacturable 32 nm SOI CMOS Technology","authors":"T. Chavan, S. Dutta, N. Mohapatra, U. Ganguly","doi":"10.1109/DRC.2018.8442229","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442229","url":null,"abstract":"Human brain is a seemingly random network of $sim 10^{11}$ neurons connected by $sim 10^{14}$ synapses, beating today's best supercomputers by $sim 10^{6}times$ in energy efficiency (fig. 1). Hardware realization of such a biological network requires compact, energy efficient electronic analogs on a sufficiently matured technology. Several CMOS based analog/digital implementations suffer from large area and power consumption [1] [2]. Non-CMOS implementation of neurons may provide area/energy efficiency, but they pose fabrication challenges [3]–[5]. Earlier, our group demonstrated an energy efficient neuron on a highly manufacturable 32 nm SOI CMOS technology [6]. Impact ionization (II) based hole storage was utilized to obtain the neuronal behavior in this compact PD-SOI neuron. However, the range of operation lies in the saturation region of the transistor. This causes large current flowing through it, which adds to the power consumption. Here, we propose tunneling based hole storage enabling equivalent functionality in the SOI neuron. Unlike II, tunneling is dominant in the sub-threshold regime. Hence, the same functionality is achievable at $10^{3}times$ lower power at sub-threshold. Thus, tunneling based neuron meets all the requirements of low energy operation, high manufacturability, and CMOS compatibility.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124811969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effects of single vacancy defects on 1/f noise in grapbene/b-BN FETs","authors":"Ting Wu, A. Alharbi, T. Taniguchi, Kenji Watanabe, D. Shahrjerdi","doi":"10.1109/DRC.2018.8442196","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442196","url":null,"abstract":"SP2 carbon materials, including carbon nanotubes and graphene, have been used extensively for making highly sensitive biochemical field-effect transistor (FET) sensors. Previous studies suggest that structural disorders in these materials enhance the device sensitivity. Despite many studies on device sensitivity in relation to structural defects, only a few studies have examined the effect of defects on low-frequency noise in graphene FETs [1]. However, no study has yet investigated the correlation between the specific type defects, e.g. single vacancy defects, and the low-frequency noise characteristics of graphene transistors. Here, we systematically study the connection between the concentration of single vacancy defects, the low-frequency noise and carrier transport in graphene FETs.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125895853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermally Aided Nonvolatile Memory Using $pmb{mathrm{ReS}_{2}}$ Transistors","authors":"Natasha Goyal, D. Mackenzie, Himani Jawa, D. H. Petersen, S. Lodha","doi":"10.1109/DRC.2018.8442168","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442168","url":null,"abstract":"Recently two-dimensional (2D) materials have attracted significant research interest for memory applications. Monolayer (MoL) as well as multilayer (ML) $mathrm{MoS}_{2}$ have been used for demonstrating thermally assisted non-volatile memories (NVM) [5], [6]. With increasing packing density of FETs on a single wafer, high performance ICs can reach an operating temperature closer to 370–530 K range [3] making it important to understand and exploit the behavioural changes in these materials at higher temperatures (HT). Thermally assisted NVM is one such application where locally generated heat is exploited to aid the switching between RESET (RST/STATE 0) and WRITE (WR/STATE 1) states [4]. In this study thermally varying hysteretic gate operation in ML $mathrm{MoS}_{2}$ and for the first time in $pmb{MLReS_{2}}$ is studied and compared for NVM application. Due to lack of interlayer coupling $mathrm{ReS}_{2}$ behaves as decoupled $mathrm{MoLs}$ making it a direct band gap material $(mathrm{E}_{mathrm{G}}sim 1.5mathrm{eV})$ for both ML and MoL [2] and hence is of interest for optoelectronic applications in $mathrm{MoL}$ as well as ML form. We demonstrate clockwise (CW) hysteresis at lower temperatures (LT) and anticlockwise (ACW) plus step like conductance crossover (STC) hysteresis at 373 K & 400 K for ML $mathrm{ReS}_{2}$ and $mathrm{MoS}_{2}$ respectively. Similar hysteresis behaviour has been previously reported for MoL Mos2 only at a very high operating temperature of 500 K [5]. STC hysteresis provides an edge over CW hysteresis at HT in terms of lower operating voltages $(mathrm{V}_{mathrm{p}-mathrm{p}})$, larger RST to WR window defined here as $Delta mathrm{V}_{mathrm{th}}/mathrm{V}_{mathrm{p}-mathrm{p}}$ (where $Delta mathrm{V}_{mathrm{th}}$ is the hysteresis width) and larger READ (RD) window. These parameters for previous NVM reports are mentioned in Table 1 and compared with this work. $pmb{ ML ReS_{2}}$ operates at much lower temperatures, lower $V_{p-p}$ and has larger WR to RST and RD windows as compared to $pmb{MoS_{2}}$.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126764383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Performance, Sub-thermionic MoS2 Transistors using Tunable Schottky Contacts","authors":"Shubhadeep Bhattacharjee, K. Ganapathi, S. Mohan, N. Bhat","doi":"10.1109/DRC.2018.8442194","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442194","url":null,"abstract":"The inability to scale $mathrm{V}_{mathrm{dd}}$ owing to the Boltzmann limit (Sub-threshold Slope $(SS)=60mathrm{mV}/mathrm{dec}$ @ 300 K) has been the primary bottleneck in obtaining power efficient scaled transistors [1]. Two-dimensional semiconductors owing to their naturally ultra-thin body offer excellent opportunities for highly scaled nano-transistors [4]. However, explorations of sub-thermionic devices on these materials have been heavily stymied owing to inefficient doping, contacts and dielectric integration. In this work, we attempt to combine the excellent SS of the TFET with the high $mathrm{I}_{mathrm{on}}$ of the thermionic MOSFET employing effective device design and materials processing. We adopt a conscious design strategy to use Schottky contacts as switching elements, which, unlike BTBT junctions allow for both thermionic (high $mathrm{I}_{mathrm{on}}$) AND tunneling (very steep SS) dominated operational modes. A plausible conduction mechanism is elucidated which agrees well with experimental results.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115215552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}