An Improved 1T-DRAM Cell Using TiO2as the Source and Drain of an n-Channel PD-SOI MOSFET

Due to fabrication challenges for the scaling of the capacitor of a conventional DRAM cell below 100 nm technology node, the concept of 1 T-DRAM cell[I] was proposed as an alternative. In all-Si 1T-DRAM cell, the body of an n-channel PD-SOI MOSFET is used as the storage node. The biggest drawback for all-Si 1 T-DRAM cell is it's low retention time which does not meet the ITRS specification (64 ms at 358 K) [2]. As a solution to this problem, we propose a novel capacitor-less 1 T-DRAM cell, where intrinsically n-type TiO2[3] is used as the sourceldrain material and silicon as the channel of an n-channel partially depleted SOI MOSFET. Large valance band offset between TiO2 and Si $(\Delta E_{V}\approx 2\ eV)$ is utilized for storing larger number of excess holes in the body for a longer time than is possible with an all-Si 1T-DRAM cell. We report an improvement in retention time as well as sense margin at both $T=300\ K$ and $T=358\ K$ for our proposed DRAM cell through well calibrated TCAD simulations [4]. The extracted retention time for the proposed TiO2 source/drain 1T-DRAM cell is 3.5 s and 160 ms at $T=300\ K$ and 358 $K$ respectively and for all-Si 1 T-DRAM cell, it is 1.5 ms and $150\ \mu s$ at $T=300\ K$ and $T=358\ K$ respectively.