High-Performance Few-Layer Tellurium CMOS Devices Enabled by Atomic Layer Deposited Dielectric Doping Technique

Tellurium (Te) is a p-type narrow bandgap (0.35 eV, direct) semiconductor with high hole mobility around 700 cm2/Vs. [1] The lattice of Te is formed by 1D helical atomic chains and the neighboring chains are interconnected by van der Waals forces as shown in Fig. 1(a) [2]. Recently a liquid-based synthesis method was proposed to produce high-quality large-area 2D tellurium films with atomic flat surfaces [1], and high-performance p-MOSFETs based on few-layer tellurium films were demonstrated with large on-state current ($(> 1$ A/mm), high on/off ratio (∼106) and great stability for over two months in air [1]. However, like most of other 2D materials, the lack of doping techniques [3], [4] to obtain its counterpart n-FETs is a major roadblock against the realization of Te CMOS or steep-slope devices. In this paper, for the first time, we demonstrated Te n-FETs enabled by atomic layer deposited (ALD) dielectric doping technique with large drive current (200 mA/mm) and reasonable on/off ratio (∼103). The n-FETs show almost symmetric operation as p-FETs and comparable field-effect mobility of 612 cm2/Vs. Using low work function metal, the on-state contact resistance is reduced to $4.3 \mathrm{k}\Omega\cdot\mu \mathrm{m}$. The impacts of oxide layer type and thickness on doping effect are also systematically studied.