2018 76th Device Research Conference (DRC)最新文献_第2页

Large Room Temperature Charge-to-Spin Conversion Efficiency in Topological Insulator/CoFeB bilayers 拓扑绝缘体/CoFeB双分子层的高室温电荷自旋转换效率

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442225

Qiming Shao, Guoqiang Yu, L. Pan, X. Che, Yabin Fan, K. Murata, Q. He, T. Nie, X. Kou, Kang L. Wang

{"title":"Large Room Temperature Charge-to-Spin Conversion Efficiency in Topological Insulator/CoFeB bilayers","authors":"Qiming Shao, Guoqiang Yu, L. Pan, X. Che, Yabin Fan, K. Murata, Q. He, T. Nie, X. Kou, Kang L. Wang","doi":"10.1109/DRC.2018.8442225","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442225","url":null,"abstract":"Heavy metals and topological insulators are promising materials for converting charge current into spin current for efficient manipulation of magnetization states in magnetic devices [1]–[5]. One of the most important parameters is the charge-to-spin conversion (CS) efficiency. Improving CS efficiency is critical for reducing write current of the emerging nonvolatile memory technology, spin-orbit torque MRAM (SOT-MRAM) [2], which provides comparable speed with SRAM but with a much higher memory capacity. Here, we measure CS efficiency in various topological insulators (TIs) using second-harmonic method (2eo-method) and obtain a record-high value 8.33±0.65 for insulating (BiSb)2 Te3 at room temperature. We first establish the consistency of CS efficiency obtained between spin-torque ferromagnetic resonance (ST-FMR) and 2eo-method. Then, we systematically investigate the CS efficiency in a bilayer consisting of a metallic Bi2Se3 and a CoFeB thin film using 2eo-method. By tuning the Fermi level of TI layer into bulk band gap using (BiSb)2 Te3, we improve the CS efficiency by an order of magnitude.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128207701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Design and Demonstration of (AlxGal-x)2O3/Ga2O3Double Heterostructure Field Effect Transistor (DHFET) (AlxGal-x)2O3/ ga2o3双异质结构场效应晶体管(DHFET)的设计与演示

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8444106

Yuewei Zhang, Zhanbo Xia, C. Joishi, S. Rajan

{"title":"Design and Demonstration of (AlxGal-x)2O3/Ga2O3Double Heterostructure Field Effect Transistor (DHFET)","authors":"Yuewei Zhang, Zhanbo Xia, C. Joishi, S. Rajan","doi":"10.1109/DRC.2018.8444106","DOIUrl":"https://doi.org/10.1109/DRC.2018.8444106","url":null,"abstract":"We report on the first demonstration of (AlxGal-x)2O3/Ga2O3 double heterostructure field effect transistor using modulation doping. $beta$ -phase Ga2O3 has emerged as a promising candidate for a wide range of device applications, including power electronic devices, radio-frequency devices and solar-blind photodetectors. The wide bandgap energy and the predicted high breakdown field, together with the availability of low-cost native substrates, make $beta$ -Ga2O3 a promising material compared to other conventional wide bandgap materials, such as GaN and SiC. The use of bulk-doped $beta$ -Ga203 channels makes it challenging to achieve device scaling. Recently, (AlxGal-x)2O3/Ga2O3 modulation doped field effect transistor structures were demonstrated as a promising candidate for electronic device applications, showing the ability to improve channel mobility, and at the same time, achieve vertical scaling. High 2DEG charge density could potentially lead to better screening of the polar-optical phonon scattering at room temperature and therefore significantly enhance the electron mobility. However, the 2DEG density that can be confined in the modulation-doped structures without the introduction of parallel channels is limited by the conduction band offset at the hetero-interface and the spacer layer thickness. In this work, a modulation-doped double heterostructure field effect transistors (DHFET) is employed to further enhance the confined 2DEG density. Its electrical characterization will be discussed in this work.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121718639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

GaN Lateral Schottky Diodes with High Baliga's Figure-of-Merit Utilizing Self-Terminated, Low Damage Anode Recessing Technology 采用自端化、低损伤阳极处理技术的高Baliga品质系数GaN横向肖特基二极管

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442184

J. Gao, Y. Jin, B. Xie, C. Wen, Y. Hao, M. Wang

{"title":"GaN Lateral Schottky Diodes with High Baliga's Figure-of-Merit Utilizing Self-Terminated, Low Damage Anode Recessing Technology","authors":"J. Gao, Y. Jin, B. Xie, C. Wen, Y. Hao, M. Wang","doi":"10.1109/DRC.2018.8442184","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442184","url":null,"abstract":"AlGaN/GaN lateral diodes on silicon are considered very promising for next generation power conversion systems owing to the excellent material properties. Typically, the anode recess is a frequently-used and effective technology in reducing the SBD's VON and $mathrm{R}_{mathrm{ON},mathrm{SP}}$ [1]. However, the rough surface morphology and poor recess depth control in common dry etching are two critical issues that would lead to an increased leakage current and premature breakdown [2]. In this report, we employ a LPCVD $mathrm{Si}_{3}mathrm{N}_{4}$ compatible self-terminated, and plasma-free recess technique in an AlGaN/GaN double channel anode-recessed SBD. The anode region is prevented from plasma bombardment and the recess could stop precisely at the upper heterojunction interface with a smooth surface morphology. The SBD with a $15 mu mathrm{m} L_{mathrm{AC}}$ exhibits a low $mathrm{R}_{mathrm{ON},mathrm{SP}}$ of $1.32 mathrm{m}Omegacdot mathrm{cm}^{2}$, a remarkable $V_{mathrm{ON}}$ uniformity and a leakage current of $sim 0.2 mu mathrm{A}/mathrm{mm}$ at −300 V. Moreover, with the assistance of high quality LPCVD $mathrm{Si}_{3}mathrm{N}_{4}$, a 1.2kV breakdown voltage and a high Baliga' $mathrm{s}$ figure-of-merit of $1.1mathrm{GW}/mathrm{cm}^{2}$ are ultimately achieved in the same device.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126458679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Silicon Carbide Power Devices: A 35 Year Journey from Conception to Commercialization 碳化硅功率器件:从概念到商业化的35年历程

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442172

B. Baliga

引用次数: 10

Domain Formation in Ferroelectric Negative Capacitance Devices 铁电负电容器件中的畴形成

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/drc.2018.8442139

M. Hoffmann, S. Slesazeck, T. Mikolajick

引用次数: 1

High performance black phosphorus field-effect transistors with vacuum-annealed low-resistance Ohmic contact 具有真空退火低电阻欧姆接触的高性能黑磷场效应晶体管

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442273

Hyunik Park, Jinho Bae, Jihyun Kim

{"title":"High performance black phosphorus field-effect transistors with vacuum-annealed low-resistance Ohmic contact","authors":"Hyunik Park, Jinho Bae, Jihyun Kim","doi":"10.1109/DRC.2018.8442273","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442273","url":null,"abstract":"Layered black phosphorus (BP) exhibits desirable properties for nano-(opto)electronic device applications such as atomically thin body, direct bandgap (0.3 eV for bulk and 2.0 eV for monolayer), high carrier mobility of ~1,000 cm2/V·s, and current on/off ratio of ~105, which trigger intensive studies since its rediscovery. [1]–[3] However, high contact resistance caused by the formation of Schottky barrier and contamination at the metal-layered BP interface poses challenges in applying BP in device applications.[4] This problem becomes more serious for short-channel devices as the contact resistance is more dominant than the channel resistance, thereby, the device performance is limited by the contact resistance. Thermal annealing has been used as a promising technique for improving the contact properties in electronic devices. However, BP is vulnerable to the ambient molecules, especially in the elevated temperature, and deliberate studies of the thermal annealing on BP-based electronic devices are required. Here, the effect of post-fabrication vacuum annealing on the performance of BP field-effect transistor (FET) was investigated.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115393521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Three-Dimensional Integration of Multi-Channel MoS2 Devices for High Drive Current FETs 高驱动电流场效应管中多通道MoS2器件的三维集成

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442137

R. Zhou, J. Appenzeller

引用次数: 5

2D Electronic Devices II 2D电子装置II

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/drc.2018.8442259

引用次数: 0

Efficient Metal-Halide Perovskite Micro Disc Lasers Integrated in a Silicon Nitride Photonic Platform 氮化硅光子平台集成高效金属卤化物钙钛矿微盘激光器

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442221

P. Cegielski, S. Neutzner, C. Porschatis, M. Gandini, D. Schall, C. Perini, J. Bolten, S. Suckow, B. Chmielak, A. Petrozza, T. Wahlbrink, M. Lemme, A. Giesecke

引用次数: 1

On the Possibility of Dynamically Tuning and Collapsing the Ferroelectric Hysteresis/Memory Window in an Asymmetric DG MOS Device: A Path to a Reconfigurable Logic-Memory Device 非对称DG MOS器件中铁电迟滞/记忆窗口动态调谐和坍缩的可能性:一条通往可重构逻辑记忆器件的路径

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442250

Nujhat Tasneem, A. Khan

引用次数: 3