On the Possibility of Dynamically Tuning and Collapsing the Ferroelectric Hysteresis/Memory Window in an Asymmetric DG MOS Device: A Path to a Reconfigurable Logic-Memory Device

Abstract

We propose a novel device architecture based on ferroelectric gated double gate metal-oxide-semiconductor structure in which the memory/hysteresis window can be tuned as well as collapsed by the back-gate (control gate). The back-gate voltage alters the capacitance of the semiconductor channel which in turn modifies the capacitance matching between the semiconductor capacitance and the ferroelectric negative capacitance leading to the dynamic tunability. Such a device concept can open up pathways for a reconfigurable fabric where logic and memory operation can be tightly integrated for data intensive computing.