An Ultra Energy Efficient Neuron enabled by Tunneling in Sub-threshold Regime on a Highly Manufacturable 32 nm SOI CMOS Technology

Abstract

Human brain is a seemingly random network of $\sim 10^{11}$ neurons connected by $\sim 10^{14}$ synapses, beating today's best supercomputers by $\sim 10^{6}\times$ in energy efficiency (fig. 1). Hardware realization of such a biological network requires compact, energy efficient electronic analogs on a sufficiently matured technology. Several CMOS based analog/digital implementations suffer from large area and power consumption [1] [2]. Non-CMOS implementation of neurons may provide area/energy efficiency, but they pose fabrication challenges [3]–[5]. Earlier, our group demonstrated an energy efficient neuron on a highly manufacturable 32 nm SOI CMOS technology [6]. Impact ionization (II) based hole storage was utilized to obtain the neuronal behavior in this compact PD-SOI neuron. However, the range of operation lies in the saturation region of the transistor. This causes large current flowing through it, which adds to the power consumption. Here, we propose tunneling based hole storage enabling equivalent functionality in the SOI neuron. Unlike II, tunneling is dominant in the sub-threshold regime. Hence, the same functionality is achievable at $10^{3}\times$ lower power at sub-threshold. Thus, tunneling based neuron meets all the requirements of low energy operation, high manufacturability, and CMOS compatibility.