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2010 IEEE Radio Frequency Integrated Circuits Symposium最新文献

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A high quality factor varactor technology evaluation 一种高品质因子变容技术评价
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477308
R. Debroucke, S. Jan, J. Larchanche, C. Gaquière
{"title":"A high quality factor varactor technology evaluation","authors":"R. Debroucke, S. Jan, J. Larchanche, C. Gaquière","doi":"10.1109/RFIC.2010.5477308","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477308","url":null,"abstract":"Providing a high quality factor scalable varactor in an integrated technology is a wager. How to insure that your device will give the highest quality factor possible? In order to response this questions, we let the bases of a varactor gauge combining electrical performance and geometrical sizes. Giving a targeted capacitance, it could furnish a qualitive idea of the adequacy with technology performance. It could furnish also a indicator for comparison with other devices. As example of varactor gauge application, we present a comparison between two diode varactor devices in two BiCMOS technologies.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128079793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
RF benchmark tests for compact MOS models 紧凑型MOS模型的射频基准测试
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477292
G. Smit, A. Scholten, D. Klaassen
{"title":"RF benchmark tests for compact MOS models","authors":"G. Smit, A. Scholten, D. Klaassen","doi":"10.1109/RFIC.2010.5477292","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477292","url":null,"abstract":"Next to accurate fits of measurements, smoothness, and robustness, compact MOSFET models should ideally meet a large number of additional requirements. In this paper, we collect and derive a number of such demands that are important for RF-circuit applications. We present, for the first time, a derivation for the required reciprocity of capacitances at zero bias. We also derive from first principles the expected non-quasi-static behavior of a MOSFET at VDS = 0 as well as its thermal noise. This leads to a number of benchmark tests that a compact model needs to pass to ensure its suitability for RF-circuit applications. Finally, it is shown that the CMC standard model PSP satisfies all presented requirements.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130655664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A CMOS LC VCO with novel negative impedance design for wide-band operation 一种具有新颖负阻抗设计的宽带工作CMOS LC压控振荡器
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477288
Chang-Hsi Wu, Guan-Xiu Jian
{"title":"A CMOS LC VCO with novel negative impedance design for wide-band operation","authors":"Chang-Hsi Wu, Guan-Xiu Jian","doi":"10.1109/RFIC.2010.5477288","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477288","url":null,"abstract":"A 5.2 GHz CMOS LC voltage-controlled oscillator (VCO) for UWB receiver, fabricated using CMOS 0.18µm process, is presented in this paper. The tuning range of the proposed VCO is mainly broadened by novel negative resistance and tapping inductance techniques. Measured results of the proposed VCO reveal phase noise of −116.708/Hz at 1 MHz offset and tuning range of 4.567GHz∼5.832GHz (24.32%) while consuming only 3.92mW under the supply voltage of 0.8V. The core area is 0.732mm × 0.633mm.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115900955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 24-GHz low-power fully integrated receiver with image-rejection using Rich-Transformer Direct-Stacked/Coupled technique 采用富变压器直接堆叠/耦合技术的24ghz低功耗全集成图像抑制接收机
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477295
N. Shiramizu, Takahiro Nakamura, T. Masuda, K. Washio
{"title":"A 24-GHz low-power fully integrated receiver with image-rejection using Rich-Transformer Direct-Stacked/Coupled technique","authors":"N. Shiramizu, Takahiro Nakamura, T. Masuda, K. Washio","doi":"10.1109/RFIC.2010.5477295","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477295","url":null,"abstract":"We have developed a low-power, fully integrated receiver for 24-GHz ISM band wireless communication using a Rich-Transformer Direct-Stacked/Coupled (RT-DSC) technique. This technique makes it possible to reduce supply voltage and current without any performance degradation. The 24-GHz receiver circuit was fabricated using 0.18-µm SiGe BiCMOS technology. Receiver gain of 30 dB and noise figure (NF) of 5.6 dB are obtained at low power consumption of 21.5 mW. We utilized the synergistic effect of combining a narrow-band transformer and a notch filter to integrate the circuit's image rejection (IR) function. This resulted in our achieving power consumption only 30 % of that reported previously.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"388 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123252933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 40% PAE linear CMOS power amplifier with feedback bias technique for WCDMA applications 用于WCDMA应用的具有反馈偏置技术的40% PAE线性CMOS功率放大器
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477399
Hamhee Jeon, Kun-Seok Lee, O. Lee, K. An, Youngchang Yoon, Hyungwook Kim, Dong Ho Lee, Jongsoo Lee, Chang-Ho Lee, J. Laskar
{"title":"A 40% PAE linear CMOS power amplifier with feedback bias technique for WCDMA applications","authors":"Hamhee Jeon, Kun-Seok Lee, O. Lee, K. An, Youngchang Yoon, Hyungwook Kim, Dong Ho Lee, Jongsoo Lee, Chang-Ho Lee, J. Laskar","doi":"10.1109/RFIC.2010.5477399","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477399","url":null,"abstract":"A highly efficient CMOS linear power amplifier for WCDMA applications with feedback bias technique is presented. The method involves connecting the gates of common-gate devices of the driver stage and the power stage in cascode configurations by a feedback network for enhancing linearity. To achieve high efficiency and linearity simultaneously, large-signal IMD minimum (IMD sweet spot) is properly used at the desired output power level. The proposed PA was fabricated in a 0.18-µm CMOS technology. The experimental results demonstrate a gain of 26 dB, a maximum output power of 26 dBm with 46.4% of peak PAE, and a linear output power of 23.5 dBm with 40% PAE using a 3GPP WCDMA modulated signal. Both simulation and measurement results show an excellent large-signal IMD minimum at the output power using a WCDMA modulated signal.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122468038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Low-noise fractional-N PLL design with mixed-mode triple-input LC VCO in 65nm CMOS 65纳米CMOS混合模式三输入LC压控振荡器的低噪声分数n锁相环设计
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477397
Yuanfeng Sun, X. Yu, W. Rhee, Sangsoo Ko, Wooseung Choo, Byeong-ha Park, Zhihua Wang
{"title":"Low-noise fractional-N PLL design with mixed-mode triple-input LC VCO in 65nm CMOS","authors":"Yuanfeng Sun, X. Yu, W. Rhee, Sangsoo Ko, Wooseung Choo, Byeong-ha Park, Zhihua Wang","doi":"10.1109/RFIC.2010.5477397","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477397","url":null,"abstract":"This paper presents a low-noise ΔΣ fractional-N PLL utilizing a mixed-mode triple-input LC VCO. An analog dual-path VCO control relaxes the nonlinearity problem of the ΔΣ fractional-N PLL, while a combination of discrete and continuous tuning methods for coarse-tuning control significantly alleviates the noise coupling problem caused by the high gain coarse-tuning path. A 3.6GHz ΔΣ fractional-N PLL implemented in 65nm CMOS exhibits nearly −100dBc/Hz in-band noise contribution and −53dBc in-band fractional spur performances from a 1.8GHz carrier.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128471419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 6.1 GS/s 52.8 mW 43 dB DR 80 MHz bandwidth 2.4 GHz RF bandpass ΔΣ ADC in 40 nm CMOS 6.1 GS/s 52.8 mW 43 dB DR 80 MHz带宽2.4 GHz RF带通ΔΣ 40 nm CMOS ADC
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477374
J. Ryckaert, A. Geis, L. Bos, G. van der Plas, J. Craninckx
{"title":"A 6.1 GS/s 52.8 mW 43 dB DR 80 MHz bandwidth 2.4 GHz RF bandpass ΔΣ ADC in 40 nm CMOS","authors":"J. Ryckaert, A. Geis, L. Bos, G. van der Plas, J. Craninckx","doi":"10.1109/RFIC.2010.5477374","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477374","url":null,"abstract":"A 2.4 GHz 4th order BP ΔΣ ADC is presented. The feedforward topology uses Gm-LC resonators that can be calibrated in frequency. The quantizer is split in 6 interleaved comparators to relax speed. Clocked at 6.1 GHz, it achieves a DR of 43 dB in 80 MHz consuming 52.8 mW. Implemented in 40 nm CMOS, it achieves a FoM of 3.6 pJ/conv. step, which is to date the lowest published value for RF BP ADCs.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126476635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
An 80GHz range synchronized push-push oscillator for automotive radar application 用于汽车雷达的80GHz范围同步推推振荡器
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477324
C. Ameziane, T. Taris, Y. Deval, D. Belot, R. Plana, J. Bégueret
{"title":"An 80GHz range synchronized push-push oscillator for automotive radar application","authors":"C. Ameziane, T. Taris, Y. Deval, D. Belot, R. Plana, J. Bégueret","doi":"10.1109/RFIC.2010.5477324","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477324","url":null,"abstract":"In this paper, we present an injection locked oscillator operating at 81GHz and intended for automotive radar applications. The topology of the voltage controlled oscillator (VCO) is based on a push-push topology suitable for millimeter wave applications. The synthesis technique is based on a synchronization throw an external sub-harmonic signal. The reference signal, around 8GHz, is converted before being injected into the oscillator by inductive coupling. We describe in this work, the details of this synchronization technique. The synthesizer is implemented in a 0.13μm SiGe BiCMOS technology from STMicroelectronics. The synchronized oscillator exhibits a maximum locking range of 3GHz from 81GHz to 84GHz and a phase noise around -108dBc/Hz at 10MHz from the carrier frequency. The 1.1mm2 circuit chip consumes 60mA under 1.8V supply.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"32 10S 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125925697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
An all-digital offset PLL architecture 全数字偏移锁相环结构
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477376
R. Staszewski, S. Vemulapalli, K. Waheed
{"title":"An all-digital offset PLL architecture","authors":"R. Staszewski, S. Vemulapalli, K. Waheed","doi":"10.1109/RFIC.2010.5477376","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477376","url":null,"abstract":"We propose an all-digital offset PLL architecture in which the RF oscillator output is frequency translated through rotation of its quadrature phases before being fed back for the phase comparison with the frequency reference. This eliminates spurious tones caused by the finite resolution of the phase detection process when the synthesized frequency is very close to the integer-N multiple of the reference frequency. The phase detection in the ADPLL is performed by a time-to-digital converter (TDC), whose typical resolution of 10–30 ps is sufficient for the GSM-quality RF operation. While the TDC quantization noise does not normally produce significant phase noise degradation, the near-integer-N condition makes the loop ill-behaved such that the total quantization energy falls close to dc and will not get filtered by the loop filter. In addition, due to the frequency relationship change between aggressors and victims, an important class of spurs due to parasitic coupling is also eliminated. The hardware overhead is very small and the digital implementation does not degrade other RF parameters. The technique is validated in a 65-nm CMOS transceiver.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117145330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A wideband millimeter-wave frequency doubler-tripler in 0.13-µm CMOS 一种0.13µm CMOS的宽带毫米波倍频三倍器
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477262
Shadi Saberi Ghouchani, J. Paramesh
{"title":"A wideband millimeter-wave frequency doubler-tripler in 0.13-µm CMOS","authors":"Shadi Saberi Ghouchani, J. Paramesh","doi":"10.1109/RFIC.2010.5477262","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477262","url":null,"abstract":"A combined frequency doubler and tripler is proposed for wideband millimeter wave frequency generation in CMOS. The circuit consists of a push-push FET frequency doubler along with a single-balanced mixer based frequency tripler. The frequency doubler-tripler can generate frequencies in the range of 23–48 GHz with more than −20dBm output power into 50Ω. The conversion gains of the doubler and tripler are measured to be −2.6dB and −12.3 dB, respectively, with a 0dBm input at 14.4GHz. Fabricated in 0.13-µm CMOS, the circuit has an active area of 600×440 µm2. The frequency multipliers consume 12.6mW dc power from 1.2V supply, while the output buffers consume 11.9mW.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130646111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
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