6.1 GS/s 52.8 mW 43 dB DR 80 MHz带宽2.4 GHz RF带通ΔΣ 40 nm CMOS ADC

2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI:10.1109/RFIC.2010.5477374

J. Ryckaert, A. Geis, L. Bos, G. van der Plas, J. Craninckx

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引用次数: 26

摘要

介绍了一种2.4 GHz四阶BP ΔΣ ADC。前馈拓扑使用Gm-LC谐振器，可以在频率上进行校准。量化器被分割成6个交错的比较器来放松速度。时钟频率为6.1 GHz，在80 MHz时达到43 dB的DR，消耗52.8 mW。在40nm CMOS中实现，FoM为3.6 pJ/conv。步骤，这是迄今为止RF BP adc的最低公布值。

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A 6.1 GS/s 52.8 mW 43 dB DR 80 MHz bandwidth 2.4 GHz RF bandpass ΔΣ ADC in 40 nm CMOS

A 2.4 GHz 4th order BP ΔΣ ADC is presented. The feedforward topology uses Gm-LC resonators that can be calibrated in frequency. The quantizer is split in 6 interleaved comparators to relax speed. Clocked at 6.1 GHz, it achieves a DR of 43 dB in 80 MHz consuming 52.8 mW. Implemented in 40 nm CMOS, it achieves a FoM of 3.6 pJ/conv. step, which is to date the lowest published value for RF BP ADCs.

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2010 IEEE Radio Frequency Integrated Circuits Symposium

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