Yuanfeng Sun, X. Yu, W. Rhee, Sangsoo Ko, Wooseung Choo, Byeong-ha Park, Zhihua Wang
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Low-noise fractional-N PLL design with mixed-mode triple-input LC VCO in 65nm CMOS
This paper presents a low-noise ΔΣ fractional-N PLL utilizing a mixed-mode triple-input LC VCO. An analog dual-path VCO control relaxes the nonlinearity problem of the ΔΣ fractional-N PLL, while a combination of discrete and continuous tuning methods for coarse-tuning control significantly alleviates the noise coupling problem caused by the high gain coarse-tuning path. A 3.6GHz ΔΣ fractional-N PLL implemented in 65nm CMOS exhibits nearly −100dBc/Hz in-band noise contribution and −53dBc in-band fractional spur performances from a 1.8GHz carrier.
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