An all-digital offset PLL architecture

We propose an all-digital offset PLL architecture in which the RF oscillator output is frequency translated through rotation of its quadrature phases before being fed back for the phase comparison with the frequency reference. This eliminates spurious tones caused by the finite resolution of the phase detection process when the synthesized frequency is very close to the integer-N multiple of the reference frequency. The phase detection in the ADPLL is performed by a time-to-digital converter (TDC), whose typical resolution of 10–30 ps is sufficient for the GSM-quality RF operation. While the TDC quantization noise does not normally produce significant phase noise degradation, the near-integer-N condition makes the loop ill-behaved such that the total quantization energy falls close to dc and will not get filtered by the loop filter. In addition, due to the frequency relationship change between aggressors and victims, an important class of spurs due to parasitic coupling is also eliminated. The hardware overhead is very small and the digital implementation does not degrade other RF parameters. The technique is validated in a 65-nm CMOS transceiver.