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Inverse modeling of sub-100nm MOSFET with PDE-constrained optimization 基于pde约束优化的亚100nm MOSFET逆建模
2011 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2011-10-06 DOI: 10.1109/SISPAD.2011.6034965
Chen Shen, D. Gong
{"title":"Inverse modeling of sub-100nm MOSFET with PDE-constrained optimization","authors":"Chen Shen, D. Gong","doi":"10.1109/SISPAD.2011.6034965","DOIUrl":"https://doi.org/10.1109/SISPAD.2011.6034965","url":null,"abstract":"The inverse modeling of MOSFET aims to extract the process and device parameters of a CMOS technology from electrical test data, such as the I–V curves. Unlike the parameter extraction for compact models, inverse modeling calculates the electrical characteristics with TCAD simulation instead of the analytical formulae of compact models (e.g. BSIM4). The parameters extracted from inverse modeling can be either the process parameters (e.g. Dose, energy, annealing time, etc.), or the device parameters (oxide thickness, peak doping concentration, char. length of Gaussian doping, etc.). Obviously, inverse modeling is an optimization problem to minimize the error between the simulated and the measured electrical characteristics.","PeriodicalId":264913,"journal":{"name":"2011 International Conference on Simulation of Semiconductor Processes and Devices","volume":"163 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126840882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Development of SF6/O2/Si plasma etching topography simulation model using new flux estimation method 基于新通量估计方法的SF6/O2/Si等离子体刻蚀形貌模拟模型的建立
2011 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2011-10-06 DOI: 10.1109/SISPAD.2011.6035063
Tomoharu Ikeda, H. Saito, F. Kawai, K. Hamada, T. Ohmine, H. Takada, V. Deshpande
{"title":"Development of SF6/O2/Si plasma etching topography simulation model using new flux estimation method","authors":"Tomoharu Ikeda, H. Saito, F. Kawai, K. Hamada, T. Ohmine, H. Takada, V. Deshpande","doi":"10.1109/SISPAD.2011.6035063","DOIUrl":"https://doi.org/10.1109/SISPAD.2011.6035063","url":null,"abstract":"A new topography simulation method has been developed for SF6/O2/Si plasma etching of trench gates in IGBTs. This method calculates the ion and fluorine radical flux parameters required for the topography simulation from the etching rate and selectivity obtained from simple basic experiments. The O radical flux was assumed as a function of the operating conditions and the function form was determined by fitting etching profiles of the topography simulation to those of the experiment. The model used in the topography simulation was improved in terms of the etching yield dependence on the ion incidence angle. As a result, a large variety of profiles could be simulated accurately under different operational conditions.","PeriodicalId":264913,"journal":{"name":"2011 International Conference on Simulation of Semiconductor Processes and Devices","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124423184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Effects of atomic disorder on carrier transport in Si nanowire transistors 原子无序对硅纳米线晶体管载流子输运的影响
2011 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2011-10-06 DOI: 10.1109/SISPAD.2011.6035041
H. Minari, T. Zushi, Takanobu Watanabe, Y. Kamakura, N. Mori
{"title":"Effects of atomic disorder on carrier transport in Si nanowire transistors","authors":"H. Minari, T. Zushi, Takanobu Watanabe, Y. Kamakura, N. Mori","doi":"10.1109/SISPAD.2011.6035041","DOIUrl":"https://doi.org/10.1109/SISPAD.2011.6035041","url":null,"abstract":"Effects of oxidation-process-induced atomic disorder on extended electronic states in the channel region of narrow Si nanowire (NW) field-effect-transistors (FETs) are theoretically investigated by using the molecular dynamics, empirical tight-binding, and non-equilibrium Green's function methods. Simulation results show that the injection velocity in n-type Si NW FETs is less affected by the disorder compared to p-type devices, which can be attributed to differences in the in-plane carrier profile.","PeriodicalId":264913,"journal":{"name":"2011 International Conference on Simulation of Semiconductor Processes and Devices","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127397564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multilevel simulation for the investigation of fast diffusivity paths 研究快速扩散路径的多水平模拟
2011 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2011-10-06 DOI: 10.1109/SISPAD.2011.6035068
H. Ceric, R. Orio, F. Schanovsky, W. Zisser, Siegfried Selberherr
{"title":"Multilevel simulation for the investigation of fast diffusivity paths","authors":"H. Ceric, R. Orio, F. Schanovsky, W. Zisser, Siegfried Selberherr","doi":"10.1109/SISPAD.2011.6035068","DOIUrl":"https://doi.org/10.1109/SISPAD.2011.6035068","url":null,"abstract":"The reliability of interconnects in modern integrated circuits is determined by the magnitude and direction of the effective valence for electromigration (EM). The effective valence depends on local atomistic configurations of fast diffusivity paths such as metal interfaces, dislocations, and the grain boundary; therefore, microstructural variations lead to a statistically pre-dictable behavior for the EM life time. Quantum mechanical investigations of EM have been carried out on an atomistic level in order to obtain numerically efficient methods for calculating the effective valence. The results of ab initio calculations of the effective valence have been used to parameterize the continuum-level electromigration model and the kinetic Monte Carlo model. The impact of fast diffusivity paths on long term EM behavior is demonstrated with these models.","PeriodicalId":264913,"journal":{"name":"2011 International Conference on Simulation of Semiconductor Processes and Devices","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129309741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of worst-case hot-carrier degradation conditions in the case of n- and p-channel high-voltage MOSFETs n沟道和p沟道高压mosfet最坏情况下热载流子退化情况分析
2011 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2011-10-06 DOI: 10.1109/SISPAD.2011.6035066
I. Starkov, H. Ceric, S. Tyaginov, T. Grasser, H. Enichlmair, Jong-Mun Park, C. Jungemann
{"title":"Analysis of worst-case hot-carrier degradation conditions in the case of n- and p-channel high-voltage MOSFETs","authors":"I. Starkov, H. Ceric, S. Tyaginov, T. Grasser, H. Enichlmair, Jong-Mun Park, C. Jungemann","doi":"10.1109/SISPAD.2011.6035066","DOIUrl":"https://doi.org/10.1109/SISPAD.2011.6035066","url":null,"abstract":"We have analyzed the worst-case conditions of hot-carrier induced degradation for high-voltage n- and p-MOSFETs with our model. This model is based on the evaluation of the carrier distribution function along the Si/SiO2 interface, i.e. on thorough consideration of carrier transport. The distribution function obtained by means of a full-band Monte-Carlo device simulator is used to calculate the acceleration integral, which controls how effectively the carriers are breaking Si - H bonds. Therefore, we analyze the worst-case conditions using this integral as a criterion. We compare the simulated picture with the experimental one and conclude that the model fits the experimental data precisely well for both transistor types.","PeriodicalId":264913,"journal":{"name":"2011 International Conference on Simulation of Semiconductor Processes and Devices","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127532676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Analysis of geometrical structure and transport property in InAs/Si heterojunction nanowire tunneling field effect transistors InAs/Si异质结纳米线隧穿场效应晶体管几何结构及输运特性分析
2011 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2011-10-06 DOI: 10.1109/SISPAD.2011.6034961
Y. Miyoshi, M. Ogawa, S. Souma, Hajime Nakamura
{"title":"Analysis of geometrical structure and transport property in InAs/Si heterojunction nanowire tunneling field effect transistors","authors":"Y. Miyoshi, M. Ogawa, S. Souma, Hajime Nakamura","doi":"10.1109/SISPAD.2011.6034961","DOIUrl":"https://doi.org/10.1109/SISPAD.2011.6034961","url":null,"abstract":"Band-to-band tunneling (BTBT) field-effect transistors (FETs) is one of the promisng strategies in reducing the leakage current and improving the subthreshold characteristics compared with the conventional metal-oxide-semiconductor field-effect transistors (MOSFETs). However, BTBT-FETs have an intrinsic drawback of small on-current. We explore numerically the possibility of using the InAs/Si heterojunction nanowire (NW) to resolve such intrinsic difficulty in BTBT-FETs, and found that the use of the InAs/Si heterojunction nanowire is advantageous in increasing the on-current compared with the Si homojunction nanowires.","PeriodicalId":264913,"journal":{"name":"2011 International Conference on Simulation of Semiconductor Processes and Devices","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126726496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Nanostructuration of Graphene Nanoribbons for thermoelectric applications 热电应用中石墨烯纳米带的纳米结构
2011 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2011-10-06 DOI: 10.1109/SISPAD.2011.6034960
F. Mazzamuto, J. Saint-Martin, V. Nguyen, Y. Apertet, C. Chassat, P. Dollfus
{"title":"Nanostructuration of Graphene Nanoribbons for thermoelectric applications","authors":"F. Mazzamuto, J. Saint-Martin, V. Nguyen, Y. Apertet, C. Chassat, P. Dollfus","doi":"10.1109/SISPAD.2011.6034960","DOIUrl":"https://doi.org/10.1109/SISPAD.2011.6034960","url":null,"abstract":"Atomistic simulations of electron and phonon transport are performed within the non-equilibrium Green's function formalism to analyze the thermal and electrical properties of graphene nanoribbons (GNRs). We predict that by patterning GNRs properly, a strong enhancement of thermoelectric properties can be achieved. From the study of edge orientation effects, we propose a strategy likely to degrade the thermal conductance while retaining high electronic conductance and thermopower. An effect of resonant tunneling of electrons is evidenced in mixed GNRs consisting in alternate zigzag and armchair sections or in perfect GNRs with vacancies. Combining these effects, an optimized structure able to provide a high thermoelectric factor of merit ZT exceeding unity at room temperature is demonstrated","PeriodicalId":264913,"journal":{"name":"2011 International Conference on Simulation of Semiconductor Processes and Devices","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124828442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The flexible compact SOI-MOSFET model HiSIM-SOI valid for any structural types 灵活紧凑的SOI-MOSFET模型HiSIM-SOI适用于任何结构类型
2011 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2011-10-06 DOI: 10.1109/SISPAD.2011.6034968
M. Miyake, S. Kusu, H. Kikuchihara, A. Tanaka, Y. Shintaku, M. Ueno, J. Nakashima, U. Feldmann, H. Mattausch, M. Miura-Mattausch, T. Yoshida
{"title":"The flexible compact SOI-MOSFET model HiSIM-SOI valid for any structural types","authors":"M. Miyake, S. Kusu, H. Kikuchihara, A. Tanaka, Y. Shintaku, M. Ueno, J. Nakashima, U. Feldmann, H. Mattausch, M. Miura-Mattausch, T. Yoshida","doi":"10.1109/SISPAD.2011.6034968","DOIUrl":"https://doi.org/10.1109/SISPAD.2011.6034968","url":null,"abstract":"We have developed the HiSIM-SOI model which is a complete surface-potential-based compact model valid for any structural variations of SOI-MOSFETs. This work focuses on how to calculate the three surface-potential values at the FOX/SOI-layer surface, the SOI-layer/BOX surface, and the BOX/substrate surface. The Newton iteration with three variables is investigated. With good initial guesses of the three surface potentials, accurate solutions are obtained with small number of iterations. Dynamically switching depletion modes are achieved by considering all possible charges induced within the device explicitly. Furthermore, SPICE simulation of 100-stage NAND chains demonstrates stable convergence of the surface-potential Newton iteration for any bias conditions.","PeriodicalId":264913,"journal":{"name":"2011 International Conference on Simulation of Semiconductor Processes and Devices","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123740203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
TCAD challenges and some Fraunhofer solutions TCAD挑战和一些弗劳恩霍夫解决方案
2011 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2011-10-06 DOI: 10.1109/SISPAD.2011.6035028
J. Lorenz
{"title":"TCAD challenges and some Fraunhofer solutions","authors":"J. Lorenz","doi":"10.1109/SISPAD.2011.6035028","DOIUrl":"https://doi.org/10.1109/SISPAD.2011.6035028","url":null,"abstract":"In order to meet its industrial target to reduce the development time and costs for new semiconductor technologies, devices and circuits, TCAD must meet various challenges which are outlined in the ITRS. After a short outline of these challenges, related results obtained at Fraunhofer for the simulation of lithography and other topography steps, dopant diffusion/activation, device architectures and impact of process variations are summarized.","PeriodicalId":264913,"journal":{"name":"2011 International Conference on Simulation of Semiconductor Processes and Devices","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122679021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Properties of InAs- and silicon-based ballistic spin field-effect transistors InAs和硅基弹道自旋场效应晶体管的性能
2011 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2011-10-06 DOI: 10.1109/SISPAD.2011.6035049
D. Osintsev, V. Sverdlov, A. Makarov, S. Selberherr
{"title":"Properties of InAs- and silicon-based ballistic spin field-effect transistors","authors":"D. Osintsev, V. Sverdlov, A. Makarov, S. Selberherr","doi":"10.1109/SISPAD.2011.6035049","DOIUrl":"https://doi.org/10.1109/SISPAD.2011.6035049","url":null,"abstract":"We investigate the transport properties of ballistic spin field-effect transistors. The transistor characteristics are examined for a broad range of parameters including the semiconductor channel length, the conduction band mismatch between the channel and the contacts, the strength of the spin-orbit interaction, and the magnetic field. We show that temperature exerts a significant influence on the device characteristics. For the InAs-based transistors a shorter channel is preferred for potential operations at room temperature. For the silicon-based transistors we demonstrate that the [100] fin orientation displays a stronger dependence of the magnetoresistanse on the strength of the spin-orbit interaction and is therefore best suited for practical realization of the silicon spin transistor.","PeriodicalId":264913,"journal":{"name":"2011 International Conference on Simulation of Semiconductor Processes and Devices","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132202999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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