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12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)最新文献

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Dielectric charge traps. A new structure element for power devices 介电电荷陷阱。一种新型动力器件结构元件
12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI: 10.1109/ISPSD.2000.856807
H. Kapels, R. Plikat, D. Silber
{"title":"Dielectric charge traps. A new structure element for power devices","authors":"H. Kapels, R. Plikat, D. Silber","doi":"10.1109/ISPSD.2000.856807","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856807","url":null,"abstract":"The progress in SOI technologies, especially SIMOX and Silicon Direct Bonding, suggests a new type of structural element which could improve device blocking behavior in various aspects. A novel structure element for realizing high breakdown voltages in power devices is analyzed using numerical simulations. We propose dielectric structures which in strong vertical fields collect majority or minority carriers. These structures enable surprising new solutions for various problems. Improved high voltage field plates, surface field reduced Schottky rectifiers, dynamic buffers and Ron improved unipolar devices can be achieved.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130325495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
A fast-switching SOI SA-LIGBT without NDR region 一种无NDR区的快速开关SOI sa灯
12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI: 10.1109/ISPSD.2000.856793
Jung-Hoon Chul, D. Byeon, J. Oh, M. Han, Yearn-Ik Choi
{"title":"A fast-switching SOI SA-LIGBT without NDR region","authors":"Jung-Hoon Chul, D. Byeon, J. Oh, M. Han, Yearn-Ik Choi","doi":"10.1109/ISPSD.2000.856793","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856793","url":null,"abstract":"The SOI separated shorted-anode LIGBT (SSA-LIGBT) has been investigated by experiments and numerical device simulations. In order to suppresses the negative differential resistance regime which is the inherent drawback of the shorted anode LIGBT (SA-LIGBT), the SSA-LIGBT increases the pinch resistance by employing the highly resistive n-drift region as an electron conduction path. The SSA-LIGBT shows a remarkably decreased on-state voltage drop when compared with the conventional SA-LIGBT and shows a one-order faster turn-off time than that of the LIGBT.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116880978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Analysis of the forward biased safe operating area of the super junction MOSFET 超结MOSFET正向偏置安全工作区域分析
12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI: 10.1109/ISPSD.2000.856773
B. Zhang, Z. Xu, A.Q. Huang
{"title":"Analysis of the forward biased safe operating area of the super junction MOSFET","authors":"B. Zhang, Z. Xu, A.Q. Huang","doi":"10.1109/ISPSD.2000.856773","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856773","url":null,"abstract":"In this paper, the forward biased safe operating area (FBSOA) of the super junction MOSPET (also called CoolMOS) is studied. The FBSOA of a 600-V CoolMOS transistor-SPP20N60S5 is experimentally obtained. The FBSOA characteristic and the FBSOA failure mechanisms are analyzed in detail with the help of numerical simulations. The impact of the charge imbalance on the FBSOA is also studied in this work.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134543463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Advanced on-chip polysilicon CMOS analog and driver circuit technology for intelligent discrete devices 先进的片上多晶硅CMOS模拟和驱动电路技术，用于智能离散器件
12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI: 10.1109/ISPSD.2000.856780
T. Matsudai, T. Kojima, A. Nakagawa
{"title":"Advanced on-chip polysilicon CMOS analog and driver circuit technology for intelligent discrete devices","authors":"T. Matsudai, T. Kojima, A. Nakagawa","doi":"10.1109/ISPSD.2000.856780","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856780","url":null,"abstract":"In this paper, we investigate the analog and driver circuit performances of 0.8 /spl mu/m gate length polysilicon CMOS fabricated on a thermal oxide film. Especially, we report the capability of load short-circuit protection circuit and high-side driver circuit. For the first time, it is found that the improved polysilicon analog circuits works sufficiently rapidly to protect high voltage power devices. It was experimentally confirmed that a 20 A/600 V high power IGBT can be driven and safely protected from load short-circuit failure by the polysilicon circuits within 200 nsec. It was also shown that a polysilicon high-side driver circuit with a charge pump successfully switched on a 25 A/60 V MOSFET within 130 /spl mu/sec.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117042568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Beyond Y2K: technology convergence as a driver of future low-voltage power management semiconductors 超越千年虫:技术融合作为未来低压电源管理半导体的驱动因素
12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI: 10.1109/ISPSD.2000.856764
R.K. Williams
{"title":"Beyond Y2K: technology convergence as a driver of future low-voltage power management semiconductors","authors":"R.K. Williams","doi":"10.1109/ISPSD.2000.856764","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856764","url":null,"abstract":"Convergence of computing consumer, and communication products into multifunction portables (e.g. Internet cell phones) is driving today's electronics toward a unified chip set concept sharing common power architectures. These converging specifications allow analog and power management ICs and discretes to migrate into older mid-to-deep submicron DRAM fabs, enjoying significant chip shrinks, speed increases, switch resistance reduction, higher functionality and lower manufacturing costs. Low thermal budget processes, CMP, 3D structures, ultra-shallow junctions and planarized interconnects are promising and beneficial byproducts of this evolution. The world's first production 45 Mcell/cm/sup 2/ (287 Mcell/in/sup 2/) vertical 30 V power TrenchDMOS is illustrative of technology convergence in power management semiconductors.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114396522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Experimental results and simulation analysis of 250 V super trench power MOSFET (STM) 250v超级沟功率MOSFET (STM)的实验结果及仿真分析
12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI: 10.1109/ISPSD.2000.856777
T. Nitta, T. Minato, M. Yano, A. Uenisi, M. Harada, S. Hine
{"title":"Experimental results and simulation analysis of 250 V super trench power MOSFET (STM)","authors":"T. Nitta, T. Minato, M. Yano, A. Uenisi, M. Harada, S. Hine","doi":"10.1109/ISPSD.2000.856777","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856777","url":null,"abstract":"We propose a new structure of power MOSFET, i.e. Super Trench power MOSFET (STM). Instead of a conventional n-drift layer, STM has vertical P and N layers formed within mesa regions between adjacent trenches filled with insulator. The P and N stripe structure relaxes the electric field in off-state and makes possible a lower specific on-resistance (Ron, sp) than that of the conventional MOSFET. We fabricated a 250 V STM for the first time with only one additional mask over the conventional DMOS process, and the measured data show high breakdown voltage with highly doped n drift layer. The device simulation results show it should be possible to lower the Ron, sp to 5 m/spl Omega/cm/sup 2/ for a breakdown voltage of 300 V.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"235 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116158262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 51
Evaluation of 600 V/100 A NPT-IGBT with a non-self-align shallow p-well formation techniques 600 V/100 A NPT-IGBT非自对准浅p井地层技术评价
12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI: 10.1109/ISPSD.2000.856812
M. Otsuki, S. Momota, M. Kirisawa, H. Wakimoto, Y. Seki
{"title":"Evaluation of 600 V/100 A NPT-IGBT with a non-self-align shallow p-well formation techniques","authors":"M. Otsuki, S. Momota, M. Kirisawa, H. Wakimoto, Y. Seki","doi":"10.1109/ISPSD.2000.856812","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856812","url":null,"abstract":"Experimental results of planer gate IGBTs fabricated with newly developed a non-self-align shallow p-well formation technique are presented. The 600 V/100 A NPT-IGBT shows the on-state voltage drop of about 1.7 V, which is more than 0.4 V reduction compared to the conventional devices. The average short circuit withstand capability of about 30 /spl mu/sec was obtained without external current limiting functions.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114239772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Over 2000 V FLR termination technologies for SiC high voltage devices 用于SiC高压器件的2000 V以上FLR终端技术
12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI: 10.1109/ISPSD.2000.856817
H. Onose, S. Oikawa, T. Yatsuo, Y. Kobayashi
{"title":"Over 2000 V FLR termination technologies for SiC high voltage devices","authors":"H. Onose, S. Oikawa, T. Yatsuo, Y. Kobayashi","doi":"10.1109/ISPSD.2000.856817","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856817","url":null,"abstract":"The Field Limiting Ring (FLR) termination structures are examined in order to confirm the high voltage technology of SiC diodes and FETs. Elemental devices with planar FLR terminations are fabricated and their reverse I-V characteristics are determined using 4H n-type SiC. First demonstrations of breakdown voltages higher than 2000 V are succeeded by using FLR terminations. Optimal FLR spacing of the boron termination is wider than that of the aluminum case. This difference is considered to show that the lateral diffusion is remarkable for the process using boron implantation.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"29 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125278178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
1500 V, 4 amp 4H-SiC JBS diodes 1500 V, 4安培4H-SiC JBS二极管
12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI: 10.1109/ISPSD.2000.856782
R. Singh, S. Ryu, J. Palmour, A. Hefner, J. Lai
{"title":"1500 V, 4 amp 4H-SiC JBS diodes","authors":"R. Singh, S. Ryu, J. Palmour, A. Hefner, J. Lai","doi":"10.1109/ISPSD.2000.856782","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856782","url":null,"abstract":"This paper reports the detailed design, fabrication and characterization of 1500 V, 4 Amp 4H-SiC JBS diodes. 2D device simulations show that a grid spacing of 4 /spl mu/m results in the most optimum trade-off between the on-state and off-state characteristics. JBS diodes with linear and honeycombed p/sup +/ grids, Schottky diodes and implanted PiN diodes fabricated alongside show that while 4H-SiC JBS diodes behave similar to Schottky diodes in the on-state and switching characteristics, they show reverse characteristics similar to PiN diodes. Measurements on 4H-SiC JBS diodes indicate that the reverse recovery time (/spl tau//sub n/) and associated losses are near zero even at a rev. dI/dt of 75 A//spl mu/sec. Based on measured waveforms, detailed loss models on diode switching were established for a high frequency switching power supply efficiency evaluation. A DC/DC converter efficiency improvements of 3-6% were obtained over the fastest, lower blocking voltage silicon diode when operated in the 100-200 kHz range.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126541104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
4.5 kV novel high voltage high performance SiC-FET "SIAFET" 4.5 kV新型高压高性能SiC-FET (SIAFET)
12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI: 10.1109/ISPSD.2000.856783
Y. Sugawara, M. Asano, R. Singh, J. Palmour, D. Takayama
{"title":"4.5 kV novel high voltage high performance SiC-FET \"SIAFET\"","authors":"Y. Sugawara, M. Asano, R. Singh, J. Palmour, D. Takayama","doi":"10.1109/ISPSD.2000.856783","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856783","url":null,"abstract":"A novel high voltage SiC MOS device named SIAFET (Static induction Injected Accumulated FET) is proposed, which has no pn junction in its on-current flow path and has a conductivity modulation by carriers injected from a p+ buried gate. SIAFET with blocking voltage (BV) of 5500 V and specific on-resistance RonS (without the conductivity modulation) of 57 m/spl Omega/cm/sup 2/ was designed by using the 6200 V mesa JTE and was fabricated using 4H-SiC substrates. Its basic operation has been confirmed for the first time and it has been demonstrated that its RonS has been shown to reduce to less than 1/6 by SIAFET action. Although its achieved BV is relatively low (2030 V and 4580 V) and its RonS is relatively high (172 m/spl Omega/cm/sup 2/ and 387 m/spl Omega/cm/sup 2/), RonS of 4580 V SiC-SIAFET is less than 1/25 that of the theoretical RonS limit of Si-MOSFET for this BV.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122760735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
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