1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

A single-chip 20 channel speech spectrum analyzer 单片20通道语音频谱分析仪

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1984-02-01 DOI: 10.1109/ISSCC.1984.1156579

Y. Kuraishi, K. Nakayama, K. Miyadera

引用次数: 3

Fine line NMOS transresistance amplifiers 细线NMOS跨阻放大器

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1984.1156584

A. Abidi, B. Kasper, R. Kushner

引用次数: 4

A 128K word × 8b DRAM 128K字×8 b DRAM

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1984.1156592

S. Suzuki, M. Nakao, T. Takeshima, M. Yoshida, M. Kikuchi, K. Nakamura

引用次数: 2

512K EPROMs

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/isscc.1984.1156665

D. Rinerson, M. Ahrens, Jih Lein, B. Venkatesh, Tien Lin, P. Song, S. Longcor, L. Shen, D. Rogers, M. Briner

引用次数: 3

A 46ns 256K CMOS SRAM 一个46ns 256K CMOS SRAM

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1984.1156711

M. Isobe, J. Matsunaga, T. Sakurai, T. Ohtani, K. Sawada, H. Nozawa, T. Iizuka, S. Kohyama

引用次数: 8

An ECL field programmable logic array 一个ECL现场可编程逻辑阵列

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1984.1156685

C. Schmitz, H. Hingarh, M. Brown, Hang Kwan, J. Vithayathil

引用次数: 4

A CMOS/SOS multiplier CMOS/SOS乘法器

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1984.1156597

Jun Iwamura, K. Suganuma, M. Kimura, S. Taguchi

{"title":"A CMOS/SOS multiplier","authors":"Jun Iwamura, K. Suganuma, M. Kimura, S. Taguchi","doi":"10.1109/ISSCC.1984.1156597","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156597","url":null,"abstract":"A CMOS/SOS 16b x 16b parallel multiplier with a chip using a modified array to speed arithmetic, performing a 16b x 16b multiplication typically in 27ns, while dissipating 150mW power, will be reported. Functions and pin configuration of the chip have been designed to have upward compatibility with commercially available LSI multipliers*. Figure la shows a fraction of the multiplier array which uses a modified array technique’ in contrast to a conventional carry save adder shown in b . The array consists of odd rows and even rows. Sum and carry signals generated by an odd row are pansferred to the next odd row, and those of an even row are concurrently transferred to the next even row. Therefore, two pairs of sum and carry signal streams are prepared in the array in parallel. In the following stage, the sum of odd rows and of the even rows are added together to produce a final product. Since this modified array has reduced. the number of addition stages by about one half compared to the conventional carry save adder method, the maximum number of adder stages in a column required to accomplish any mode of 16b x 16b multiplication is only nine.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121194961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 23

Distributed cascode amplifier and noise figure modeling of an arbitrary amplifier configuration 分布式级联放大器和任意放大器配置的噪声图建模

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1984.1156587

D. Dawson, M. Salib, L. Dickens

引用次数: 8

A VLSI communication processor designed for testability 为可测试性而设计的VLSI通信处理器

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1984.1156646

S. Sacarisen, M. Stambaugh, P. Lou, A. Khosrovi, Ki Chang

引用次数: 4

A CMOS CCD video delay line CMOS CCD视频延迟线

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1984.1156604

M. Sato, S. Ogasawara, K. Suzuki

{"title":"A CMOS CCD video delay line","authors":"M. Sato, S. Ogasawara, K. Suzuki","doi":"10.1109/ISSCC.1984.1156604","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156604","url":null,"abstract":"in Figure 2. The delay time difference between two CCD registers (684.5b and 2b) produces a 6 3 . 5 ~ delay time. The IC, using the 684.5b/Zb CCD registers independently can serve as two switchable delay lines, or as two registers together to form a comb filter. The amplitude required for the input clock signal is only lOOmV p-p. Up to 1 V p-p video signals can pass through the delay line without appreciable distortion. The output circuit (Figure 3) contains a double-stage source follower, followed by double stage of a sample and hold circuit and a CMOS inverter amplifier. I n the CMOS circuit the inverter amplifiers have two configurations and are applied in the output circuit. Consequently, a level shift circuit is not necessary between the two inverters. The CMOS inverter amplifier has a wide dynamic range. A comparison of the CMOS inverter amplifier and a conventional N-channel amplifier, together with their total harmonic distortion, is shown in Figure 4. The gain of the amplifier is determined by the transconductance ratio of N-channel and P-channel MOS FETs. Compared to single N-channel inverters, CMOS inverters are free from back gate bias effects. Thus, it is possible to construct high-gain and high-speed amplifiers with CMOS inverters. Characteristic degradations, due to the sample and hold pulse timing, are suppressed by using two-stage sample and hold circuits. The sampling pulse amplitudes are 9V p-p in the first stage and 5V p-p in the second stage insuring a good output signal dynamic range, and a reduction of the sampling pulse coupling.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127868007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5