C. Schmitz, H. Hingarh, M. Brown, Hang Kwan, J. Vithayathil
{"title":"一个ECL现场可编程逻辑阵列","authors":"C. Schmitz, H. Hingarh, M. Brown, Hang Kwan, J. Vithayathil","doi":"10.1109/ISSCC.1984.1156685","DOIUrl":null,"url":null,"abstract":"This paper will cover a 4ns compatible ECL field programmable logic array, organized16×24×(8+\\bar{8})with true and complement output. Features include vertical junction fuses as programmable elements and built-in test.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"An ECL field programmable logic array\",\"authors\":\"C. Schmitz, H. Hingarh, M. Brown, Hang Kwan, J. Vithayathil\",\"doi\":\"10.1109/ISSCC.1984.1156685\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper will cover a 4ns compatible ECL field programmable logic array, organized16×24×(8+\\\\bar{8})with true and complement output. Features include vertical junction fuses as programmable elements and built-in test.\",\"PeriodicalId\":260117,\"journal\":{\"name\":\"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1984.1156685\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1984.1156685","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper will cover a 4ns compatible ECL field programmable logic array, organized16×24×(8+\bar{8})with true and complement output. Features include vertical junction fuses as programmable elements and built-in test.