512K EPROMs

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/isscc.1984.1156665

D. Rinerson, M. Ahrens, Jih Lein, B. Venkatesh, Tien Lin, P. Song, S. Longcor, L. Shen, D. Rogers, M. Briner

引用次数: 3

Abstract

EPROMs utilizing double polysilicon floating gate technology that achieve bit densities through 64Kb to 512Kb and access times of 150ns will be reported. Through the use of an NMOS process with 1.7μm design rules, a minimum cell size of 36.6μm2has been obtained.

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采用双多晶硅浮栅技术的eprom，比特密度可达64Kb至512Kb，访问时间可达150ns。通过采用1.7μm设计规则的NMOS工艺，获得了最小电池尺寸36.6μm2。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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