A CMOS/SOS multiplier

Abstract

A CMOS/SOS 16b x 16b parallel multiplier with a chip using a modified array to speed arithmetic, performing a 16b x 16b multiplication typically in 27ns, while dissipating 150mW power, will be reported. Functions and pin configuration of the chip have been designed to have upward compatibility with commercially available LSI multipliers*. Figure la shows a fraction of the multiplier array which uses a modified array technique’ in contrast to a conventional carry save adder shown in b . The array consists of odd rows and even rows. Sum and carry signals generated by an odd row are pansferred to the next odd row, and those of an even row are concurrently transferred to the next even row. Therefore, two pairs of sum and carry signal streams are prepared in the array in parallel. In the following stage, the sum of odd rows and of the even rows are added together to produce a final product. Since this modified array has reduced. the number of addition stages by about one half compared to the conventional carry save adder method, the maximum number of adder stages in a column required to accomplish any mode of 16b x 16b multiplication is only nine.