A 128K word × 8b DRAM

THE DESIGN OF A 128K word x 8b MOS DRAM, which has a 120ns access time and 290mW power dissipation, will be described. In realizing the chip, 1p.m NMOS technology, with double level aluminum construction, has been utilized. The chip is non-address-multiplexed and accomodated in a 30-pin package; Figure 1. The RAM has operated on all memory cells. One of the major purposes of the project to be reported was to establish and demonstrate low-noise circuit technology. A dummy reversal technique, was adopted to introduce the half Vcc bit line precharge technique with dummy cells. A noise evaluation simulation in cell-array designing, based on a three dimensional capacitance calculation, was also conducted. Extensive utilization of double-level aluminum wiring, not only in the memory cell array, but also in peripheral circuits, has reduced substantially circuit noise. Moreover, it has drastically cut the time required for chip layout, while the cell occupation ratio is over 60%.