An ECL field programmable logic array

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156685

C. Schmitz, H. Hingarh, M. Brown, Hang Kwan, J. Vithayathil

引用次数: 4

Abstract

This paper will cover a 4ns compatible ECL field programmable logic array, organized16×24×(8+\bar{8})with true and complement output. Features include vertical junction fuses as programmable elements and built-in test.

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一个ECL现场可编程逻辑阵列

本文将介绍一个4ns兼容的ECL现场可编程逻辑阵列organized16×24×(8+\bar{8})，具有真值和补值输出。功能包括垂直结熔断器作为可编程元件和内置测试。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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