{"title":"Comparing fail-safe microcontroller architectures in light of IEC 61508","authors":"R. Mariani, P. Fuhrmann","doi":"10.1109/DFT.2007.63","DOIUrl":"https://doi.org/10.1109/DFT.2007.63","url":null,"abstract":"In this paper, an overview is given on the main architectures used in the automotive to implement fail-safe microcontrollers. The concept of a new HW-centric, distributed and optimized architecture is also presented. In light of the IEC 61508 norm for safety related electronic systems, a comparisons between these different architectures is done based on a reference design. The paper concludes discussing how the presented architectures can be extended to become fail-functional","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134099467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hiroshi Takahashi, Y. Higami, Toru Kikkawa, T. Aikyo, Y. Takamatsu, H. Yotsuyanagi, M. Hashizume
{"title":"Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines","authors":"Hiroshi Takahashi, Y. Higami, Toru Kikkawa, T. Aikyo, Y. Takamatsu, H. Yotsuyanagi, M. Hashizume","doi":"10.1109/DFT.2007.11","DOIUrl":"https://doi.org/10.1109/DFT.2007.11","url":null,"abstract":"In order to ensure high quality of DSM circuits, testing for the open defect in the circuits is necessary. However, the modeling and techniques for test generation for open faults have not been established yet. In this paper, we propose a method for generating tests and diagnostic tests based on a new open fault model. Firstly, we show a new open fault model with considering adjacent lines [9]. Under the open fault model, we reveal more about the conditions to excite the open fault. Next we propose a method for generating tests for open faults by using a stuck-at fault test with don't cares. We also propose a method for generating a diagnostic test that can distinguish the pair of open faults. Finally, experimental results show that (1) the proposed method is able to achieve 100% fault coverages for almost all benchmark circuits and (2) the proposed method is able to reduce the number of indistinguished open fault pairs.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124368711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Functional Verification based Fault Injection Environment","authors":"A. Benso, A. Bosio, S. Carlo, R. Mariani","doi":"10.1109/DFT.2007.31","DOIUrl":"https://doi.org/10.1109/DFT.2007.31","url":null,"abstract":"Fault injection is needed for different purposes such as analyzing the reaction of a system in a faulty environment or validating fault-detection and/or fault-correction techniques. In this paper we propose a simulation-based fault injection tool able to work at different abstraction levels and with user-defined fault models. By exploiting the facilities provided by a functional verification environment it allows to speed up the entire fault injection process: from the creation of the workload to the analysis of the results of injection campaigns. Moreover, the adoption of techniques to optimize the fault list significantly reduces the simulation time. Being the tool targeted to the validation of dependable systems, it includes a way to extract information from the Failure Mode and Effect Analysis and to correlate fault injection results with estimates.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114185652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Matrosova, Ekaterina Loukovnikova, S. Ostanin, Alexandra Zinchuk, E. Nikolaeva
{"title":"Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs","authors":"A. Matrosova, Ekaterina Loukovnikova, S. Ostanin, Alexandra Zinchuk, E. Nikolaeva","doi":"10.1109/DFT.2007.42","DOIUrl":"https://doi.org/10.1109/DFT.2007.42","url":null,"abstract":"A combinational circuit is derived with covering the proper Shared ROBDD by CLBs in the frame of FPGA technology. Single stuck-at faults at the CLBs poles and multiple faults constituted from such single stuck-at faults are considered. It is shown that the test pattern as for single stuck-at fault so for multiple fault there always exists. The test pattern for a multiple fault is the special test pattern for the special single stuck-at fault forming the multiple one. Test for all multiple faults is derived from any test for all single stuck-at faults. The length of the multiple faults test is linear function of the single faults test length. A multiple fault test is the one of high quality. In particular SEU and bridge faults may manifest themselves as multiple faults at the CLBs poles. Deriving test for all multiple faults was executed for the certain bench-marks. For them the length of the multiple faults test is about the twice length of the single faults test.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128625059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model","authors":"R. Ghaida, P. Zarkesh-Ha","doi":"10.1109/DFT.2007.12","DOIUrl":"https://doi.org/10.1109/DFT.2007.12","url":null,"abstract":"During semiconductor manufacturing, particles undesirably depose on the surface of the wafer causing \"open\" and \"short\" defects to interconnects. In this paper, a third type of defects called \"interconnect narrowing\" defect is defined. Interconnect narrowing occurs when a defect intervenes the lithographic printing of interconnects causing the formation of a narrow interconnect. The narrow sites of defective interconnects favor electromigration that makes narrow interconnects more likely to induce a chip failure than regular interconnects. In this paper, a layout sensitivity model accounting for narrowing defects is derived. A methodology for predicting the probability of narrow interconnects using the sensitivity model is then proposed. The layout sensitivity model for narrow interconnects is tested and compared to actual and simulated data. Our layout sensitivity model for narrow interconnects predicts the probability of narrowing with 3.1% error, on average. The model is then combined with electromigration constraints to predict mean-time-to-failure of chips manufactured in future technology down to 32 nm node. The paper concludes with some other possible applications of the narrow interconnect predictive model.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131403105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Soft Error Hardening for Asynchronous Circuits","authors":"W. Kuang, C.M. Ibarra, P. Zhao","doi":"10.1109/DFT.2007.15","DOIUrl":"https://doi.org/10.1109/DFT.2007.15","url":null,"abstract":"As the devices are scaling down, the combinational logic will become susceptible to soft errors. The conventional soft error tolerant methods for soft errors on combinational logic do not provide enough high soft error tolerant capability with reasonably small performance penalty. This paper investigates the feasibility of designing quasi-delay insensitive (QDI) asynchronous circuits for high soft error tolerance. We analyze the behavior of Null Convention Logic circuits in the presence of particle strikes, and propose a novel technique to improve the robustness of threshold gates, which are basic components in NCL, against particle strikes by using Schmitt trigger circuit and resizing the feedback transistor. Experimental results show that the proposed threshold gates do not generate soft errors under the strike of a particle within a normal energy range if a proper transistor size is applied. The penalties, such as delay and power consumption, are also presented.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115252619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/DFT.2007.10","DOIUrl":"https://doi.org/10.1109/DFT.2007.10","url":null,"abstract":"We describe a method for on-line testing of delay faults based on the comparison of output responses of identical circuits. The method allows one of the circuits to participate in useful computations during the testing process, while the other circuit must be idle. We refer to this method as semi-concurrent on-line testing. While unknown input vectors are applied to the circuit that participates in useful computations, the proposed method applies modified vectors to the idle circuit. In this way, different conditions are created for the detection of delay faults, allowing identical delay faults that affect both circuits to be detected. In designing the modified vectors, we ensure that the expected fault free responses of the two circuits are identical. We also ensure that the hardware for modifying the vectors applied to the idle circuit will be easy to implement on-chip.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"125 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120867073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Effective Checkpoint and Rollback Using Hardware/OS Collaboration","authors":"P. Michele, L. Regis","doi":"10.1109/DFT.2007.48","DOIUrl":"https://doi.org/10.1109/DFT.2007.48","url":null,"abstract":"We present a technique that achieves an effective and complete checkpoint and rollback by exploiting collaborations between the operating system and the cache system in a microprocessor-based environment. That scheme allows overheads to be kept extremely low, while ensuring a great generality.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126473179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Probabilistic Analysis of a Molecular Quantum-Dot Cellular Automata Adder","authors":"T. J. Dysart, P. Kogge","doi":"10.1109/DFT.2007.39","DOIUrl":"https://doi.org/10.1109/DFT.2007.39","url":null,"abstract":"Since nanoelectronic devices are likely to be defective and error-prone, developing an understanding of circuit reliabilities and critical components will be required. To this end, this paper examines reliability considerations of several sample circuits when implemented in a molecular QCA technology. Probabilistic transfer matrices are used to analyze an XOR, crossover, adder, and an adder using triple modular redundancy. This provides insight in answering how reliable emerging circuit components must be to have a reliable circuit and which of these components are the most critical. As will be shown, component error rates must be at or below 10~4 for an adder to function with 99% reliability and that the straight wire and majority gate are the most critical components to each circuit's reliability. It is also shown that the common assumption made in triple modular redundancy theory that only gates fail is insufficient for QCA.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134532349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Spare Parts in Analog Circuits: a Filter Example","authors":"Erik Schüler, A. Souza, L. Carro","doi":"10.1109/DFT.2007.13","DOIUrl":"https://doi.org/10.1109/DFT.2007.13","url":null,"abstract":"Spare parts technique has been widely used in digital designs. As memory cells are more susceptible to defects and faults than logic cells, redundancy has been extensively used for enhancing defect and fault tolerance through repair by spare replacement. The technique also aims yield increase, and points to be a very good solution since density integration gets ever higher. In this work, we propose the use of spare parts to develop reliable analog circuits, thus increasing fault tolerance by choosing among many identical blocks, the best ones that will compose the circuit. An example using a mixed-signal FIR filter is presented, showing that the technique can easily be adapted to help increase yield of analog circuits, too.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123494000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}