22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)最新文献_第3页

On-Line Periodic Self-Testing of High-Speed Floating-Point Units in Microprocessors 微处理器中高速浮点单元的在线周期性自检

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI: 10.1109/DFT.2007.32

G. Xenoulis, M. Psarakis, D. Gizopoulos, A. Paschalis

{"title":"On-Line Periodic Self-Testing of High-Speed Floating-Point Units in Microprocessors","authors":"G. Xenoulis, M. Psarakis, D. Gizopoulos, A. Paschalis","doi":"10.1109/DFT.2007.32","DOIUrl":"https://doi.org/10.1109/DFT.2007.32","url":null,"abstract":"On-line periodic testing of microprocessors is a viable low-cost alternative for a wide variety of embedded systems which cannot afford hardware or software redundancy techniques but necessitate the detection of intermittent or permanent faults. Low-cost, on-line periodic testing has been previously applied to the integer datapaths of microprocessors but not to their high-performance real number processing counterparts consisting of sophisticated high-speed floating-point (FP) units. In this paper, we present, an effective on-line periodic self-testing methodology for high-speed FP units and demonstrate it on high-speed FP adders/subtracters of both single and double precision. The proposed self-test code development methodology leads to compact self-test routines that exploit the integer part of the processors instruction set architecture to apply test sets to the FP subsystem periodically. The periodic self-test routines exhibit very low memory storage requirements along with a very small number of memory references which are both fundamental requirements for on-line periodic testing. A comprehensive set of experiments on both single and double precision FP units including pipelined versions, and on a RISC processor with a complete FP unit demonstrate the efficacy of the methodology in terms of very high fault coverage and low memory footprint thus rendering the proposed methodology highly appropriate for on-line periodic testing.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"1228 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120939767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Evaluation of Single Event Upset Mitigation Schemes for SRAM based FPGAs using the FLIPPER Fault Injection Platform 基于FLIPPER故障注入平台的SRAM fpga单事件干扰缓解方案评估

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI: 10.1109/DFT.2007.45

M. Alderighi, F. Casini, S. D'Angelo, M. Mancini, S. Pastore, G. Sechi, R. Weigand

引用次数: 116

RAM-based fault tolerant state machines for FPGAs 基于ram的fpga容错状态机

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI: 10.1109/DFT.2007.33

L. Frigerio, F. Salice

引用次数: 11

Fault Tolerant SoC Architecture Design for JPEG2000 using Partial Reconfigurability 基于部分可重构的JPEG2000容错SoC架构设计

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI: 10.1109/DFT.2007.37

A. Doumar, Kentaroh Katoh, Hideo Ito

{"title":"Fault Tolerant SoC Architecture Design for JPEG2000 using Partial Reconfigurability","authors":"A. Doumar, Kentaroh Katoh, Hideo Ito","doi":"10.1109/DFT.2007.37","DOIUrl":"https://doi.org/10.1109/DFT.2007.37","url":null,"abstract":"In this paper, we present the design of a new architecture tolerating faults for the Image compression standard JPEG2000. The proposed fault tolerant design is based on adding a new reconfigurable core to the rest of the cores of the SoC. When a fault happens, it is tolerated using this reconfigurable core. The paper explains the hardware architecture allowing this inter-core communication toward fault tolerance. The target is to achieve a good reliability by this fault tolerance strategy and in the same time achieve the required speed allowing to the JPEG2000 to deal with video rather than still Image compression. The high speed is implemented using an optimized data organization and memories arrangement for the computation consuming blocks of the JPEG2000. The operating speed of the proposed architecture is 125 MHz for ALTERA FPGA implementation. The proposed architecture has increased the speed by a factor of 1.5, when compared to similar memory requiring architectures and decreased the memory requirement by a factor of 1.2, when compared to similar speed requiring architectures. Additionally, the proposed architecture achieves 91.45% fault coverage and it requires only 21% hardware overhead. The architecture has an optimum latency of 78.8 seconds corresponding to an optimum test sequence of n=985. The VHDL implementation of the six blocks of JPEG2000, corresponding to the full chain, has been developed and successfully validated on various types of ALTERA FPGA.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117233372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections 基于多级故障注入的高级加密标准寄存器级保护技术评价

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI: 10.1109/DFT.2007.41

P. Maistri, P. Vanhauwaert, R. Leveugle

引用次数: 14

Fault Tolerant Source Routing for Network-on-chip 片上网络的容错源路由

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI: 10.1109/DFT.2007.14

Young Bok Kim, Yong-Bin Kim

引用次数: 68

Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Model 基于高级故障模型的NoC交换机在线故障检测与诊断

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI: 10.1109/DFT.2007.55

Armin Alaghi, Naghmeh Karimi, Mahshid Sedghi, Z. Navabi

引用次数: 80

A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip 多处理器片上系统可靠性评估与增强框架

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI: 10.1109/DFT.2007.35

G. Beltrame, C. Bolchini, L. Fossati, A. Miele, D. Sciuto

引用次数: 11

Nanofabric PLA architecture with Redundancy Enhancement 具有冗余增强的纳米聚乳酸结构

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI: 10.1109/DFT.2007.36

M. Joshi, W. Al-Assadi

引用次数: 5

Checker Design for On-line Testing of Xilinx FPGA Communication Protocols Xilinx FPGA通信协议在线测试检查器设计

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI: 10.1109/DFT.2007.21

M. Straka, Jiri Tobola, Z. Kotásek

引用次数: 10