RAM-based fault tolerant state machines for FPGAs

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI:10.1109/DFT.2007.33

L. Frigerio, F. Salice

引用次数: 11

Abstract

The paper presents a solution to protect FSM implemented on FPGAs from SEU, exploiting the embedded memories available in modern FPGA devices and a Hamming code for error detection and correction. A fault tolerant FSM architecture is presented, along with a generator to automate the FSM implementation. Experimental results show that this solution is particularly suited especially when FSMs with a large number of outputs are present in the target design.

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基于ram的fpga容错状态机

本文利用现代FPGA器件的嵌入式存储器和汉明码进行错误检测和纠错，提出了一种保护FPGA上实现的FSM不受SEU干扰的解决方案。提出了一个容错的FSM架构，以及一个自动实现FSM的生成器。实验结果表明，该方法特别适用于具有大量输出的fsm的目标设计。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)

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