22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)最新文献_第2页

Estimating Error Propagation Probabilities with Bounded Variances 有界方差下误差传播概率的估计

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI: 10.1109/DFT.2007.51

H. Asadi, M. Tahoori, C. Tirumurti

引用次数: 7

Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations 提高管道电路对电源或温度变化的容忍度

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI: 10.1109/DFT.2007.60

J. Semião, J. Rodríguez-Andina, F. Vargas, Marcelino B. Santos, I. Teixeira, João Paulo Teixeira

引用次数: 8

Timing-Aware Diagnosis for Small Delay Defects 小延迟缺陷的时序感知诊断

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI: 10.1109/DFT.2007.30

T. Aikyo, Hiroshi Takahashi, Y. Higami, Junichi Ootsu, Kyohei Ono, Y. Takamatsu

引用次数: 12

Production Yield and Self-Configuration in the Future Massively Defective Nanochips 未来大规模缺陷纳米芯片的生产良率与自构形

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI: 10.1109/DFT.2007.34

P. Zając, J. Collet

引用次数: 21

Analysis of Specified Bit Handling Capability of Combinational Expander Networks 组合扩展器网络指定位处理能力分析

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI: 10.1109/DFT.2007.52

A. Jas, S. Patil

引用次数: 0

An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains 基于SBST和扫描链的soc过渡延迟故障诊断方法

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI: 10.1109/DFT.2007.47

Jorge Luis Lagos-Benites, D. Appello, P. Bernardi, M. Grosso, D. Ravotto, E. Sánchez, M. Reorda

{"title":"An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains","authors":"Jorge Luis Lagos-Benites, D. Appello, P. Bernardi, M. Grosso, D. Ravotto, E. Sánchez, M. Reorda","doi":"10.1109/DFT.2007.47","DOIUrl":"https://doi.org/10.1109/DFT.2007.47","url":null,"abstract":"In this paper, a Software-Based Diagnosis (SBD) procedure suitable for SoCs is proposed to tackle the diagnosis of transition-delay faults. The illustrated methodology takes advantage of an initial Software-Based Self-Test (SBST) test set and of the scan-chains included in the final SoC design release. In principle, the proposed methodology consists in partitioning the considered SBST test set in several slices, and then proceeding to the evaluation of the diagnostic ability owned by each slice with the aim of discarding diagnosis-ineffective test programs portions. The proposed methodology is aimed to provide precise feedback to the failure analysis process focusing the systematic timing failures characteristic of new technologies. Experimental results show the effectiveness and feasibility of the proposed approach on a suitable SoC test vehicle including an 8-bit microcontroller, 4 SRAM memories and an arithmetic core, manufactured by STMicroelectronics, whose purpose is to provide precise information to the failure analysis process. The reached diagnostic resolution is up to the 99.75%, compared to the 93.14% guaranteed by the original SBST procedure.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"371 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132775914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing 基于增强扫描延迟故障检测的软错误硬化锁存方案

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI: 10.1109/DFT.2007.44

Takashi Ikeda, K. Namba, Hideo Ito

引用次数: 2

Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories 矩阵码:SRAM存储器的多比特容错方法

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI: 10.1109/DFT.2007.29

C. Argyrides, H. Zarandi, D. Pradhan

引用次数: 47

Reconstruction of Erasure Correcting Codes for Dependable Distributed Storage System without Spare Disks 无备盘可靠分布式存储系统的Erasure纠错码重构

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI: 10.1109/DFT.2007.26

H. Kaneko, E. Fujiwara

{"title":"Reconstruction of Erasure Correcting Codes for Dependable Distributed Storage System without Spare Disks","authors":"H. Kaneko, E. Fujiwara","doi":"10.1109/DFT.2007.26","DOIUrl":"https://doi.org/10.1109/DFT.2007.26","url":null,"abstract":"Demand is increasing for large-scale dependable storage systems for use in data-intensive servers, such as database and multimedia servers. Conventional dependable disk arrays utilize erasure correcting code to recover lost data stored on failed disks, and require two types of redundant disks: check disks to store check bits, and spare disks to replace failed disks. To reduce the number of redundant disks, this paper proposes a distributed storage system that does not require spare disks. Specifically, the proposed system replaces a failed disk with a check disk rather than with a spare disk. Erasure correction capability of the system gradually degrades with accumulation of failed disks. This paper proposes a reconstruction method for the parity-check matrix of low-density triple-erasure correcting code. Evaluation of the mean time to data loss (MTTDL) shows that, for a storage system with 120 information disks, the proposed storage system with 21 check disks gives an MTTDL of 7.9 x 104 years, while a conventional system with 26 redundant disks gives an MTTDL of 5.8 x 101 years, where the mean time to failure of each disk is 0.5 x 106 years and the maintenance interval of each system is 5,376 hours (i.e., 32 weeks).","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116637285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

On-Line Periodic Self-Testing of High-Speed Floating-Point Units in Microprocessors 微处理器中高速浮点单元的在线周期性自检

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI: 10.1109/DFT.2007.32

G. Xenoulis, M. Psarakis, D. Gizopoulos, A. Paschalis

{"title":"On-Line Periodic Self-Testing of High-Speed Floating-Point Units in Microprocessors","authors":"G. Xenoulis, M. Psarakis, D. Gizopoulos, A. Paschalis","doi":"10.1109/DFT.2007.32","DOIUrl":"https://doi.org/10.1109/DFT.2007.32","url":null,"abstract":"On-line periodic testing of microprocessors is a viable low-cost alternative for a wide variety of embedded systems which cannot afford hardware or software redundancy techniques but necessitate the detection of intermittent or permanent faults. Low-cost, on-line periodic testing has been previously applied to the integer datapaths of microprocessors but not to their high-performance real number processing counterparts consisting of sophisticated high-speed floating-point (FP) units. In this paper, we present, an effective on-line periodic self-testing methodology for high-speed FP units and demonstrate it on high-speed FP adders/subtracters of both single and double precision. The proposed self-test code development methodology leads to compact self-test routines that exploit the integer part of the processors instruction set architecture to apply test sets to the FP subsystem periodically. The periodic self-test routines exhibit very low memory storage requirements along with a very small number of memory references which are both fundamental requirements for on-line periodic testing. A comprehensive set of experiments on both single and double precision FP units including pipelined versions, and on a RISC processor with a complete FP unit demonstrate the efficacy of the methodology in terms of very high fault coverage and low memory footprint thus rendering the proposed methodology highly appropriate for on-line periodic testing.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"1228 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120939767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4