未来大规模缺陷纳米芯片的生产良率与自构形

P. Zając, J. Collet
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引用次数: 21

摘要

在这项工作中,我们解决了两个问题,即1)由大量缺陷纳米元件组成的未来芯片的弹性挑战,并在复制多核架构中组织;2)保持生产良率的问题。我们的主要建议是芯片应该在体系结构层面进行自配置,在几乎没有外部控制机制的情况下,实现核心互测隔离缺陷核心和通信自配置发现缺陷网络中的路由。我们的贡献是系统地研究了在几个不同节点连接范围从3到5的网络中,生产产量与核心故障概率(可能高达0.4)的依赖关系。结果是根据概率度量获得的,以保证输入-输出端口可以接触最小比例的节点以参与处理。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Production Yield and Self-Configuration in the Future Massively Defective Nanochips
We address two problems in this work, namely, 1) the resilience challenge in the future chips made up of massively defective nanoelements and organized in replicative multicore architectures and 2) the issue of preserving the production yield. Our main suggestion is that the chip should be self-configuring at the architectural level, enabling with almost no external control mechanisms, core mutual-test to isolate the defective core and self-configuration of communications to discover the routes in the defective network. Our contribution is a systematic study of the dependence of the production yield versus the core failure probability (possibly as high as 0.4) in several networks with different node connectivity ranging from 3 to 5. The result is obtained in terms of a probabilistic metrics to warrant that a minimal fraction of nodes can be contacted by the input-output port for participating to the processing.
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