Mahmut Yilmaz, A. Meixner, S. Ozev, Daniel J. Sorin
{"title":"Lazy Error Detection for Microprocessor Functional Units","authors":"Mahmut Yilmaz, A. Meixner, S. Ozev, Daniel J. Sorin","doi":"10.1109/DFT.2007.16","DOIUrl":"https://doi.org/10.1109/DFT.2007.16","url":null,"abstract":"We propose and evaluate the use of lazy error detection for a superscalar, out-of-order microprocessor s functional units. The key insight is that error detection is off the critical path, because an instruction s results are speculative for at least a cycle after being computed. The time between computing and committing the results can be used to lazily detect errors, and laziness allows us to use cheaper error detection logic. We show that lazy error detection is feasible, we develop a low-cost mechanism for detecting errors in adders that exploits laziness, and we show that an existing error detection scheme for multipliers can exploit laziness.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131712810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs","authors":"C. Bolchini, A. Miele, M. Santambrogio","doi":"10.1109/DFT.2007.25","DOIUrl":"https://doi.org/10.1109/DFT.2007.25","url":null,"abstract":"This paper presents the adoption of the triple modular redundancy coupled with the partial dynamic reconfiguration of field programmable gate arrays to mitigate the effects of soft errors in such class of device platforms. We propose an exploration of the design space with respect to several parameters (e.g., area and recovery time) in order to select the most convenient way to apply this technique to the device under consideration. The application to a case study is presented and used to exemplify the proposed approach.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132468313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Sharable Built-in Self-repair for Semiconductor Memories with 2-D Redundancy Scheme","authors":"Swapnil Bahl","doi":"10.1109/DFT.2007.28","DOIUrl":"https://doi.org/10.1109/DFT.2007.28","url":null,"abstract":"Newer technologies like 90 nm and 65 nm bring with them new challenges: longer time to process maturity, higher defect densities and poorer yields. The quality of test and repair determines the design's final yield and profitability. With increasing amount of memory on the chip, the need for an efficient and fast converging perfect algorithm for memory repair is increasing becoming important. In this paper, a perfect algorithm is presented for standalone repairable memories as well as for situations where redundancy is shared between different memories. The proposed BISR is composed of Built-in self-test (BIST) and built-in redundancy analysis (BIRA) module. The BISR module has a low overhead - about 5.05 % of memories area for a typical automotive chip. The proper redundancy scheme and the proposed BIRA algorithm ensure a high repair rate for the SOC and shorter test times as well as optimized area and maximum performance.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125145516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High Quality Test Vectors for Bridging Faults in the Presence of IC's Parameters Variations","authors":"M. Favalli, M. Dalpasso","doi":"10.1109/DFT.2007.19","DOIUrl":"https://doi.org/10.1109/DFT.2007.19","url":null,"abstract":"The growing dispersion of parameters in CMOS ICs poses relevant uncertainties on gate output conductances and logic thresholds that affect bridging fault (BF) detection. To analyze the quality of fault simulation and test generation tools using nominal IC parameters, we studied BF detection as a function of the standard deviation of parameters: results show that a single test vector cannot ensure acceptable escape probabilities. Conversely, the minimal number of test vectors providing null escape probability is upper-bounded with respect to variations of parameters, as verified by Monte Carlo electrical-level simulations. We propose a method to derive such minimal test sets for low frequency testing. A fault simulator and a test generator have been developed supporting the search of minimal test sets targeting a null escape probability.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125624730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Hellebrand, Christian G. Zoellin, H. Wunderlich, S. Ludwig, Torsten Coym, B. Straube
{"title":"A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction","authors":"S. Hellebrand, Christian G. Zoellin, H. Wunderlich, S. Ludwig, Torsten Coym, B. Straube","doi":"10.1109/DFT.2007.43","DOIUrl":"https://doi.org/10.1109/DFT.2007.43","url":null,"abstract":"Decreasing feature sizes have led to an increased vulnerability of random logic to soft errors. A particle strike may cause a glitch or single event transient (SET) at the output of a gate, which in turn can propagate to a register and cause a single event upset (SEU) there. Circuit level modeling and analysis of SETs provides an attractive compromise between computationally expensive simulations at device level and less accurate techniques at higher levels. At the circuit level particle strikes crossing a pn-junction are traditionally modeled with the help of a transient current source. However, the common models assume a constant voltage across the pn-junction, which may lead to inaccurate predictions concerning the shape of expected glitches. To overcome this problem, a refined circuit level model for strikes through pn-junctions is investigated and validated in this paper. The refined model yields significantly different results than common models. This has a considerable impact on SEU prediction, which is confirmed by extensive simulations at gate level. In most cases, the refined, more realistic, model reveals an almost doubled risk of a system failure after an SET.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132783690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fault Tolerant Arithmetic Operations with Multiple Error Detection and Correction","authors":"M. Valinataj, S. Safari","doi":"10.1109/DFT.2007.56","DOIUrl":"https://doi.org/10.1109/DFT.2007.56","url":null,"abstract":"Emerging technologies are dealing with more complex VLSI systems, also smaller gates and transistors which are severely influenced by electromagnetic noises and single event transient (SET) errors. Because of this increase in sensitivity and decrease in size, several soft errors might appear at the same time which can lead to multiple simultaneous errors. In this paper a concurrent and multiple error detection and correction scheme is presented for adders and multipliers based on the combination of a parity prediction scheme and a partially distributed triple modular redundancy. This scheme fits carry look-ahead and carry-skip adders/ALUs in which the carry logic represents the largest part of the circuit. The efficiency of the scheme is basically analyzed by the probability computations. The simulation of multiple random fault injection is performed to validate the predicted performance.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"354 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115925583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Masaru Fukushi, S. Horiguchi, Luke Demoracski, F. Lombardi
{"title":"A Scalable Framework for Defect Isolation of DNA Self-assemlbled Networks","authors":"Masaru Fukushi, S. Horiguchi, Luke Demoracski, F. Lombardi","doi":"10.1109/DFT.2007.38","DOIUrl":"https://doi.org/10.1109/DFT.2007.38","url":null,"abstract":"This paper presents and evaluates an approach for defect isolation of DNA self-assembled networks made of a large number of processing nodes. A previous framework based on a broadcast algorithm isolates defective nodes by using no redundancy (for the nodes) and an external defect map. Its disadvantage is the limited scalability, thus making it unsuitable for extremely large scale networks built through DNA self-assembly. Our framework improves upon the previous framework by involving three algorithmic tiers; namely, 1-hop wave expansion, efficient via placement, and unsafe node defection. The efficiency of the proposed framework is evaluated and compared with the original framework by considering large scale networks (up to 1000 times 1000 nodes), and a novel gross defect model (as well as the conventional random defect model assumed in previous manuscripts). Simulation results indicate that the proposed framework outperforms the original framework in broadcast latency and coverage, and shows excellent scalability features for DNA self-assembled nano-scale networks.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127916335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Testing of Asynchronous NULL Conventional Logic (NCL) Circuits in Synchronous-Based Desig","authors":"W. Al-Assadi, S. Kakarla","doi":"10.1109/DFT.2007.40","DOIUrl":"https://doi.org/10.1109/DFT.2007.40","url":null,"abstract":"Conventional Automatic Test Pattern Generation (ATPG) algorithms would fail when applied to asynchronous circuits due to the absence of a global clock and presence of more state holding elements that synchronize the control and data paths, leading to poor fault coverage. This paper presents a Design for Test (DFT) approach aimed at making asynchronous NCL circuits testable using conventional ATPG tools when incorporated with synchronous-based designs. The proposed approach performs scan and test points insertion on NCL designs using custom ATPG library. Experimental results show significant increase in fault coverage for NCL cyclic and acyclic pipelined designs.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127585157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Fault-Tolerant Active Pixel Sensor to Correct In-Field Hot-Pixel Defects","authors":"J. Dudas, M. L. Haye, Jenny Leung, G. Chapman","doi":"10.1109/DFT.2007.53","DOIUrl":"https://doi.org/10.1109/DFT.2007.53","url":null,"abstract":"Solid-state image sensors develop in-field defects in all common environments. Experiments have demonstrated the growth of significant quantities of hot-pixel defects that degrade the dynamic range of an image sensor and potentially limit low-light imaging. Existing software- only techniques for suppressing hot-pixels are inadequate because these defective pixels saturate at relatively low illumination levels. The redundant fault-tolerant active pixel sensor design is suggested to isolate point-like hot-pixel defects. Emulated hot-pixels have been induced in hardware implementations of this pixel architecture and measurements of pixel response indicate that it generates an accurate output signal throughout the sensor's entire dynamic range, even when standard pixels would be otherwise saturated by the hot defect. A correction algorithm repairs the final image by building a simple look-up table of illumination- response of a working pixel. In emulated hot-pixels, the true illumination value can be recovered with an error of plusmn5% under typical conditions.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133257392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jenny Leung, J. Dudas, G. Chapman, I. Koren, Z. Koren
{"title":"Quantitative analysis of in-field defects in image sensor arrays","authors":"Jenny Leung, J. Dudas, G. Chapman, I. Koren, Z. Koren","doi":"10.1109/DFT.2007.59","DOIUrl":"https://doi.org/10.1109/DFT.2007.59","url":null,"abstract":"Growth of pixel density and sensor array size increases the likelihood of developing in-field pixel defects. An ongoing study on defect development in imagers has now provided us sufficient data to be able to quantify characteristics of defect growth. Preliminary investigations have shown that defects are distributed randomly and the closest distance between two defective pixels is approximately 79-340 pixels apart. Furthermore, from an observation of 98 cluster-free defects, the diameter of the defect is estimated to be less than 2.3% of a pixel size at 99% confidence level. The fact that no defect clusters were found in the study of various digital cameras allows us to conclude that defects are not likely to be related to material degradation or imperfect fabrication but are due to environmental stress such as radiation. Furthermore, as verified by a statistical study, the absence of defect clustering provides information on the size of defects and insight into the nature of the defect development.","PeriodicalId":259700,"journal":{"name":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133757883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}