Lazy Error Detection for Microprocessor Functional Units

Abstract

We propose and evaluate the use of lazy error detection for a superscalar, out-of-order microprocessor s functional units. The key insight is that error detection is off the critical path, because an instruction s results are speculative for at least a cycle after being computed. The time between computing and committing the results can be used to lazily detect errors, and laziness allows us to use cheaper error detection logic. We show that lazy error detection is feasible, we develop a low-cost mechanism for detecting errors in adders that exploits laziness, and we show that an existing error detection scheme for multipliers can exploit laziness.