Fault Tolerant Arithmetic Operations with Multiple Error Detection and Correction

Abstract

Emerging technologies are dealing with more complex VLSI systems, also smaller gates and transistors which are severely influenced by electromagnetic noises and single event transient (SET) errors. Because of this increase in sensitivity and decrease in size, several soft errors might appear at the same time which can lead to multiple simultaneous errors. In this paper a concurrent and multiple error detection and correction scheme is presented for adders and multipliers based on the combination of a parity prediction scheme and a partially distributed triple modular redundancy. This scheme fits carry look-ahead and carry-skip adders/ALUs in which the carry logic represents the largest part of the circuit. The efficiency of the scheme is basically analyzed by the probability computations. The simulation of multiple random fault injection is performed to validate the predicted performance.