Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI:10.1109/DFT.2007.42

A. Matrosova, Ekaterina Loukovnikova, S. Ostanin, Alexandra Zinchuk, E. Nikolaeva

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引用次数: 9

Abstract

A combinational circuit is derived with covering the proper Shared ROBDD by CLBs in the frame of FPGA technology. Single stuck-at faults at the CLBs poles and multiple faults constituted from such single stuck-at faults are considered. It is shown that the test pattern as for single stuck-at fault so for multiple fault there always exists. The test pattern for a multiple fault is the special test pattern for the special single stuck-at fault forming the multiple one. Test for all multiple faults is derived from any test for all single stuck-at faults. The length of the multiple faults test is linear function of the single faults test length. A multiple fault test is the one of high quality. In particular SEU and bridge faults may manifest themselves as multiple faults at the CLBs poles. Deriving test for all multiple faults was executed for the certain bench-marks. For them the length of the multiple faults test is about the twice length of the single faults test.

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用clb覆盖共享ROBDD设计的组合电路单卡故障和多卡故障的测试生成

在FPGA技术的框架下，推导了一种由clb覆盖适当的共享ROBDD的组合电路。考虑了clb极上的单卡断和由单卡断构成的多卡断。结果表明，单卡滞故障的测试模式是存在的，多卡滞故障的测试模式是存在的。多故障测试模式是对形成多故障的特殊单卡故障的特殊测试模式。对所有多个故障的测试是从对所有单个卡在故障的任何测试派生出来的。多故障测试长度是单故障测试长度的线性函数。多故障测试是高质量的测试。特别是单单元和桥式故障可能在clb极表现为多个故障。针对特定的基准执行了针对所有多重故障的派生测试。对于他们来说，多故障测试的长度大约是单故障测试长度的两倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)

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