2009 11th Electronics Packaging Technology Conference最新文献

{"title":"Sub-modeling technique for thermo-mechanical simulation of solder microbumps assembly in 3D chip stacking","authors":"C. H. Khong, A. Yu, Xiaowu Zhang, V. Kripesh, D. Pinjala, D. Kwong, Scott Chen, Chien-Feng Chan, C. Chao, Chi-Hsin Chiu, Chih-Ming Huang, Carl Chen","doi":"10.1109/EPTC.2009.5416481","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416481","url":null,"abstract":"The submodeling technique is a powerful analysis tool. The method promotes more accurate analysis and also helps enhance productivity. It has been shown that by using displacement-force cut boundary condition method, it can be made even more versatile. The local stress phenomena of the solder microbump have been solved with this approach to demonstrate the concept. From the simulation model, it is known that the ENIG pad thickness has an effect on the aluminium pad stress in the silicon chip. This is important as the shear stress will damage the pad and circuitry on the chip. Previously this is not reported in other literatures as there is no strain gage available that can measure such a small dimension.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129073356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Method for system-level signal and power integrity modeling of high-speed electronic packages","authors":"E. Liu, Xingchang Wei, Z. Oo, Yaojiang Zhang, Wenzu Zhang, E. Li","doi":"10.1109/EPTC.2009.5416566","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416566","url":null,"abstract":"This paper reported the latest development of the modal decomposition with T-matrix method for accurate and efficient analysis of coupling of multiple vias in finite-sized multilayered parallel-plate structures. A novel boundary modeling method, named the frequency-dependent cylinder layer (FDCL), is proposed to resolve the open problem of boundary modeling associated with modal expansion methods. Moreover, a generalized T matrix model derived by the mode matching technique, is created to characterize the coupling effect for vias penetrating more than one layer in a multilayered structure. Both numerical and experimental verifications are presented to validate the new modeling methods. The above method has been incorporated into the simulation tool developed recently by us.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115915951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal resistance (Rth) enhancement by optimizing to package thermal contact","authors":"L. Sim, Darakorn Sae Le","doi":"10.1109/IEMT.2010.5746706","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746706","url":null,"abstract":"The trend for package size shrinkage has created challenges to thermal performance while improving the cost performance. When TO package size shrink by minimizing the leadframe copper usage, challenges in package warpage and thermal contact become great. TO High Creepage (a shrink version of new generation TO247) introduced difference copper thicknesses at die pad and heatsink for better material cost has created difference warpage profile which resulted loosing of the thermal contact area. The optimization of mold compound CTE for minimizing the mismatch with copper leadframe did not demonstrate positively on warpage reduction. The loss of thermal contact area and increase of thermal resistance due to warpage were characterized to determine the most effective approach to enlarge the thermal contact area. The new approach is to design-in an appropriate feature on the package to optimize the thermal contact area. The pre-shaping of package mold body as a design-in feature for compensating the loss of thermal contact area has been introduced. By this design-in feature, the package thermal contact area has been optimized and therefore the thermal performance is enhanced to the acceptable level.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117138217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of Ni-coated carbon nanotubes on interfacial intermetallic layer growth","authors":"Y.D. Han, H. Jing, S. Nai, L.Y. Xu, C. Tan, J. Wei","doi":"10.1109/EPTC.2009.5416534","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416534","url":null,"abstract":"In the present study, Ni-coated carbon nanotubes (Ni-CNTs) were incorporated into the Sn-Ag-Cu matrix, to form a composite solder. The interfacial intermetallic compound layer thickness formed on electroless nickel immersion gold (ENIG) metallized Cu substrate was determined under the as-soldered condition. It was observed that the addition of 0.01 wt.% Ni-CNTs into the Sn-Ag-Cu solder matrix, affected the formation of intermetallic compounds during the soldering reaction. For the reaction between the composite solder and the ENIG/Cu substrate, (Cu<inf>1−x</inf>Ni<inf>x</inf>)<inf>6</inf>Sn<inf>5</inf> and (Cu<inf>1−y</inf>Ni<inf>y</inf>)<inf>3</inf>Sn<inf>4</inf> were formed. The test results revealed that the thickness of interfacial IMC decreased from 2.30 μm to 1.84 μm with the addition of Ni-CNTs. Shear tests were also conducted on the as-soldered solder joints. The shear test results revealed that the composite solder joint exhibited a ~ 15% increase in yield strength and a ~ 17% increase in ultimate shear strength, as compared to its monolithic counterpart.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128045497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study of drop-performance improved lead-free solder by PCB pad finish","authors":"Y. Lee, J. Lee, J. Moon, Y. Park, K. Paik","doi":"10.1109/EPTC.2009.5416467","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416467","url":null,"abstract":"This study aimed to evaluate the drop reliability using Ag content and metal additives in a Sn-Ag-Cu system composition. In this study, the main compositions of the solder ball were Sn1.0Ag0.5Cu and Sn0.5Ag0.5Cu, respectively, and Ni and Co elements were additions a additive element. The PCB plating was used Cu-OSP, Immersion Sn, Electroplated Ni/Au, and ENEPIG (electroless Ni electroless Pd immersion Sn). The drop properties of Sn0.5Ag0.5Cu and Sn1.0Ag0.5Cu-Ni were improved by about 20% and 15%, respectively compared to that of the Sn1.0Ag0.5Cu solder ball. The Sn1.0Ag0.5Cu-Ni solder ball improved by about 15% compared to the Sn1.0Ag0.5Cu solder ball. These results are because the absorption of drop impact is increased due to the modulus and the yield strength of the solder ball are decreased by lower Ag content and Ni additives. Generally the interface IMCs between the Cu-UBM and Sn-Ag-Cu solder ball is a Cu6Sn5. But the Cu6Sn5 IMC is changed to (Cu,Ni)6Sn5 IMC, and the growth rate of the IMC is decreased by a Ni additive. The interface IMCs between Ni-UBM and the solder ball were (Cu,Ni)6Sn5, regardless of solder composition and additives. In this study, Sn0.5Ag0.5Cu-Ni solder composition was shown the best drop property that was improved about 35% compared with the Sn1.0Ag0.5Cu solder ball in all test conditions.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125770686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modelling stress in silicon with TSVs and its effect on mobility","authors":"C. Selvanayagam, Xiaowu Zhang, R. Rajoo, D. Pinjala","doi":"10.1109/EPTC.2009.5416477","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416477","url":null,"abstract":"With the most popular electronics products being the slimmest ones with the highest functionality, the ability to thin, stack and interconnect chips is becoming more important. One method to accomplish this is by using the through silicon via (TSV). This is a means of electrical connection in 3D stacked devices that saves space and shortens the electrical interconnect length, improving electrical performance [1]. Unfortunately, the large mismatch between the coefficients of thermal expansion (CTE) of copper (17.5×10−6/°C) and silicon (2.5×10−6/°C) has made the TSV a reliability concern. A mismatch in CTE translates to a mismatch in thermal strain when the wafer is subjected to large temperature loadings during fabrication [2, 3, 4]. This local thermal mismatch also induces stresses on the silicon surface around the vias which can affect the mobility of the silicon. In this study, the thermal stresses and strains induced on silicon due to the proximity of copper vias have been investigated for various geometries (via diameter, via pitch, silicon thickness, stacking layers) using finite element modeling. These results should be useful for (1) designing substrate with TSVs such that mobility in the active devices are not affected by the presence of TSVs and (2) understanding the limitations of stacking chips with respect to stress in silicon as well as joint reliability.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122226349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thin films interfacial adhesion characterization by Cross-Sectional Nanoindentation: Application to pad structures","authors":"S. Gallois-Garreignot, F. Chave, J. Gonchond, B. Gautheron, V. Fiori, D. Nélias","doi":"10.1109/EPTC.2009.5416406","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416406","url":null,"abstract":"The feature size reduction on IC chips following Moore's law leads to great integration challenge. Among others, the mechanical integrity of pad structures is particularly critical. However, to find suitable containment actions remain tricky, and a better knowledge and characterization of interfaces are then mandatory to face these problems. The Cross-Sectional Nanoindentation (CSN) is a novel method of mechanical characterization, developed by Sanchez et al. [1]. With such method, various interfaces can be characterized, at the micrometer level, in terms of adhesion energy. Its advantages compared to the well-known 4pt bending technique are numerous: a simple and fast sample preparation, direct observation of the crack path, etc. In this paper, the CSN technique is applied to discriminate and characterize the interfaces which compose a typical wire bond pad structure. More precisely, Inter-Metal Dielectric/Metal stacks, describing a pad level are tested by the mean of CSN. The exact failed interface is then determined by SEM views. However, in order to compare the interface to each others, the adhesion energies need to be known. Due to the plastic deformation of the metal during the test, Finite Element Method (F.E.M.) is required. A 2D axisymmetric model, described in [2], is used to reproduce the test. Each stack with their characteristics is simulated and an energetic quantity is calculated. Based on these values, the interfaces are finally ranked according to their mechanical reliability. Additional insights and novel findings from the state of the art are also discussed concerning both experimental and numerical aspects of the method. At last, the ability to discriminate pad structures straightforwardly by CSN is also studied. Crack behavior is investigated by S.E.M. views and a discussion is proposed concerning the most relevant criterion. Future developments concerning this method are finally described.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123246957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"2N Au wire bonding for ultra fine picth BGA","authors":"E. P. Leng, C. Yong, C. Siong, Tsuriya Masahiro, N. Vo, L. Seong, Zulkifli Mohd Faizal, Fadzli Sazilawati","doi":"10.1109/EPTC.2009.5416499","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416499","url":null,"abstract":"In this study, ultra fine pitch wire bonding on a BGA device with Al bond pad was performed to compare 2N wire with conventional 3N and 4N wires for reliability performance after thermal aging. Strip level thermal aging at 175 degree C was carried out. Wire pull test was performed after different thermal aging read point of 100hrs, 250hrs, 500hrs, 750hrs, 1000hrs, 1250hrs, 1500hrs, 1750hrs and 2000hrs to check for pull strength and lifted ball failure mode. The result had proven that 2N wire demonstrated more superior thermal aging reliability performance as compared to 3N and 4N wire. In the 2nd portion of this study, 2N wire was successfully implemented in mass production. However, several challenges were encountered due to the fact that 2N wire is much harder than conventional 3N and 4N wire which resulted in narrower process window and poorer manufacturability. This study is also aimed to share the major problems encountered and the methods to overcome those challenges during high volume manufacturing. First major challenge was lower 2nd bond peel strength due to higher sensitivity towards 2nd bond surface condition. It was found that substrate bond finger surface roughness variation is a critical factor to 2N wire bonding process. This can be improved through substrate manufacturing process optimization to reduce bond fingers surface roughness. At the same time, less optimized bonding input parameters was found to induce low wire peel strength while certain bonding input parameters was found to cause higher missing ball and short tail problem. Hence bonding parameters optimization has to be done carefully through thorough DOE and RSM studies in order to achieve higher peel strength and improve process robustness against 2nd bond surface variation. The 2nd major challenge was off-bond-pad due to harder wire that resulted in higher aluminum squeeze-out upon bonding on aluminum bond pad. It was found that proper process characterization to determine the optimum length of time needed for device expansion on heater block plus further improvement on the wire bonder and bonding parameters could help resolve this issue. The 3rd problem was higher wire stickiness due to higher sensitivity towards moisture from the environment. The main impact of wire stickiness issue was found to be higher machine stoppages due to inconsistent tail, hence resulted in off-center-ball defect. 2nd impact was higher capillary clogging which caused wire sagging and wire loop collapsing. Such wire stickiness problem could be overcome by using different wire quenching solution. In summary, 2N wire is able to improve thermal aging performance of ultra fine pitch wire bonding to meet reliability requirement as stringent as for automotive application. However, to improve mass production friendliness, careful characterization and process optimization need to be done on several areas, namely bonding surface condition, wire bonding process, as well as wire manufacturing process.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125649363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Next generation materials for thermal interface and high density energy storage applications via liquid phase sintering","authors":"J. Liu, P. Rottman, S. Dutta, P. Kumar, R. Raj, M. Renavikar, I. Dutta","doi":"10.1109/EPTC.2009.5416494","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416494","url":null,"abstract":"With the continuing increase in power dissipation requirements of electronic devices, there is a need to develop new thermal interface materials (TIM) with much higher thermal conductivity (K) than that available from conventional TIMs. Recently, liquid phase sintering (LPS) has been proposed as a new paradigm for designing next generation composite-solder TIMs with a radically different microstructure from those of conventional solder-TIMs. LPS metallic composites are also attractive as phase change materials (PCM) for thermal energy storage, where the latent heat absorbed by the one of the phases upon melting can be stored for later retrieval and/or conversion to other forms of energy. The principal advantage of metallic PCMs over other materials include: (i) much greater energy storage per unit volume than organic PCMs; and (ii) much higher thermal conductivity than both organics and inorganic salt PCMs, which allow rapid heating and energy capture. This paper presents recent results on the development of metallic TIM and PCMs for energy storage, processed by LPS of a high melting phase (HMP) with a low melting phase (LMP). A discussion of processing issues, resultant properties, and modeling results expounding the benefits of these materials is presented.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130513659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evaluation of ENEPIG substrate for handheld product application","authors":"Wayne Ng, Baterna Carlo Marbella, Ian Liang Kng Koh","doi":"10.1109/EPTC.2009.5416533","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416533","url":null,"abstract":"Electroless nickel (Ni) electroless palladium (Pd) immersion gold (Au) (ENEPIG) substrate metal finish was evaluated for suitability for handheld product. 3 main focus areas were covered in the evaluation: plating thickness measurement system, processibility and reliability. The plating thickness measurement system was established with physical analysis and mirco X-ray fluorescence. The processibility studies included Au-wire bondability on ENEPIG bond finger and lead free (Pb-free) solder paste printing on solder pad. The result showed feasibility of manufacturing electronic packages using ENEPIG substrate could be obtained with certain level of process parameters optimization. Package level reliability showed ENEPIG substrate had comparable reliability performance compared to Electrolytic NiAu / CuOSP substrate. For board level reliability, the temperature cycling on board (TCoB) and bend test (BT) showed ENEPIG substrate performed similarly but drop test (DT) showed earlier first drop to failures. The low package standoff offered acceptable number in first drop to failure despite of the application of ENEPIG substrate. Difference in substrate outer Cu layer thickness was discussed as a factor influencing drop test performance. Failure analysis (FA) found different drop testing failure modes over the ENEPIG substrate samples and CuOSP substrate samples.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122306732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}