2009 11th Electronics Packaging Technology Conference最新文献

{"title":"3D device integration","authors":"C. E. Bauer, H. Neuhaus","doi":"10.1109/EPTC.2009.5416508","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416508","url":null,"abstract":"For more than a decade the industry has recognized the power of the third dimension in package and sub-system assembly for the implementation of highly integrated mobile electronic products. Numerous approaches have been reported and demonstrated including those base on package stacking (package-on-package, origami, and edge stacked modules) and those based on die stacking (wire bond, mixed technology, edge redistribution, and through-silicon-vias). Through-silicon-vias stand out from the others as the only true 3D device integration as opposed to 3D packaging method. Consequently, through silicon via technology presents unique opportunities and challenges. For example, through-silicon-vias promise unrivaled performance improvements due to short, low impedance interconnect and high silicon efficiency. On the other hand, no other 3D approach matches the disruption of the existing food chain. This paper reviews the challenges and opportunities of 3D device integration based on through-silicon-vias in terms of, processes, applications, challenges, and intellectual property landscape.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121952569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ball impact response based on modeling techniques","authors":"K. Shinohara, Qiang Yu, M. Fujita, H. Ishii, H. Ishikawa","doi":"10.1109/EPTC.2009.5416434","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416434","url":null,"abstract":"This paper focuses on the study of the drop-impact reliability of solder joints of integrated circuit components on printed circuit boards. The impact strength and impact toughness of solder alloys are investigated by performing the ball impact test (an experimental approach). For comparison with experimental results, the fracture of a single solder joint specimen is numerically simulated using the finite element method. The fatigue strength of solder joints depends strongly on the structure of the intermetallic compound formed between solder balls and copper pads. The stiffness of all interfaces reduces due to the local stress concentration. This stress concentration occurs because of the formation of the structure between the solder ball and the substrate. The reliability of a product depends on the interface between the solder ball and the substrate.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122020701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"How to fabricate specimens for silicon-to-molding compound interface adhesion measurements","authors":"G. Schlottig, H. Pape, A. Xiao, B. Wunderle, L. Ernst","doi":"10.1109/EPTC.2009.5416523","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416523","url":null,"abstract":"We present a new method to fabricate specimen for interfacial fracture testing. It regards the interface between silicon die and epoxy molding compound (EMC). The crucial element of evaluating interfacial fracture strength is the calculation of critical fracture values. Such values can be obtained analyzing a bimaterial type of sample and by specifically inducing a delamination while monitoring conditions and loads. We use a sandwich type of sample where the epoxy molding compound encloses the silicon die. We give a detailed description of molding specimens using an established transfer molding process that has a sufficiently large cavity available. In order to prevent breakage and related residual stresses we use specific bearings to hold the silicon stripes symmetrically in place. The bearings are made out of cured EMC themselves. The samples did not break and allow for interfacial fracture characterization. For testing the specimens we used the Mixed Mode Chisel (MMC) setup, which is one of the first to at all induce and monitor delamination of the Si-EMC interface.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122623951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimization of flexible substrate for automotive LED rear-lamp","authors":"Young-Woo Kim, Min-sung Kim, Sung-Mo Park, Jae-Pil Kim, Sang-Bin Song, Nam-sun Whang, Yeongseog Lim","doi":"10.1109/EPTC.2009.5416410","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416410","url":null,"abstract":"High brightness light-emitting diodes (HB LEDs) for the automotive exterior lighting system are required to maintain the stable light output irrespective of the ambient temperature. We design the flexible substrate with the thick trace layer for heat spreader for the conventional process of printed circuit board (PCB). The performance of flexible PCB substrate with the thick copper layer of 200 um is compared with the conventional substrate attached on aluminum heat spreader of 1.5 mm and 150 W/m-K. The proposed design is analyzed in accordance with the size and thickness of heat spreader, and then the heat emission properties of the proposed substrate laminated with thick copper foil is characterized by using CFD (computational fluid dynamics) technology. The optimization of the substrate is carried out in accordance with the forward current and voltage. The thermal resistance from the top surface of LED to the plastic housing can be decreased over 1.5 times in comparison with the conventional structure while the delta forward voltage is controlled within 0. 04 V.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126369584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"3D eWLB (embedded wafer level BGA) technology for 3D-packaging/3D-SiP (Systems-in-Package) applications","authors":"S. Yoon, A. Bahr, X. Baraton, P. Marimuthu, F. Carson","doi":"10.1109/EPTC.2009.5416412","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416412","url":null,"abstract":"Demand for wafer level packaging (WLP) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. There are some restrictions in possible applications for Fan-In WLPs since global chip trends tend toward smaller chip areas with an increasing number of interconnects. The shrinkage of the pitches and pads at the chip to package interface is happening much faster than the shrinkage at the package to board interface. This interconnection gap requires fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. eWLB (embedded Wafer Level BGA) is a type of fan-out WLP that has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology. Furthermore, 3D eWLB technology enables 3D IC and 3D SiP packaging with vertical interconnection. 3D eWLB can be implemented with through silicon via (TSV) applications as well as discrete component embedding. In this paper, there will be discussion of the recent advancements in 3D eWLB packaging and integration as well as what is being envisioned and developed to address future technology requirements in 3D packaging and 3D SIP. The advantage of 3D eWLB technology and applications of 3D packaging will be presented with several examples. The process flow of 3D eWLB fabrication, assembly and packaging challenges, and performance characteristics will be also discussed.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127901900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Mid-process through silicon vias technology using tungsten metallization: Process optimazation and electrical results","authors":"G. Pares, S. Minoret, J. Lugand, S. Huet, V. Lapras, R. Anciant, D. Henry, N. Sillon, B. Dunne","doi":"10.1109/EPTC.2009.5416444","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416444","url":null,"abstract":"Through Silicon Via (TSV) is a one of the more important bricks for 3D stacking and offer different integration approaches. The via-last approach has been first introduced into production. Yet the via-first approach is also currently actively investigated since it has some advantages particularly the use of high conformal deposition materials for isolation and filling of the TSVs enabling higher density of connections or high voltage operations required for certain final product applications. We will show results on process development and integration of 70 ?m deep annular TSVs using tungsten as filling material on a dedicated test chip vehicle. First the complete process flow will be presented. Then, process development work and issues will be addressed. At first we will present developments on the annular trenches opening aiming at favorable slopes and minimum roughness. Deep RIE TSV etching process will be illustrated. For the isolation of the TSV a comparison between SACVD and DHDP deposition oxide will be then discussed. A special focus will be done on W filling sequence using multiple deposition and etch-back steps with different deposition process recipes and a final Chemical Mechanical Polishing (CMP) planarization of the TSVs. The backside process is also presented with the optimization of the back-lapping and CMP process to obtain a stress free silicon surface with no degradation of the TSVs as well as a minimum topology enabling a good back side contact. Backside interconnection is also presented featuring RDL (redistribution layer) and die-to-wafer attach with bumps technology. Then electrical characterizations will be presented. A specific test vehicle was designed to study the TSV density and proximity impact with different number of rings and ring width TSV designs. Daisy chains, specific structures to measure TSV resistance similar to Kelvin structures, interdigitated chains to measure via leakage, and special structures to stress at very high voltage (up to 1000 V), were designed. The electrical results from those specific structures will be discussed.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117229995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling solder joint fatigue in combined environmental reliability tests with concurrent vibration and thermal cycling","authors":"T. Eckert, W. Muller, N. Nissen, H. Reichl","doi":"10.1109/EPTC.2009.5416456","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416456","url":null,"abstract":"In this paper we discuss the lifetime prediction for Pb-free soldered flip chip components under combined temperature cycling (TC) and vibration loading in terms of the failure mechanisms related to solder joint fatigue. We show the results of several experiments including failure analysis and comparison of lifetime models. For this purpose finite element analyses (FEA) of the thermal cycling and vibration load are carried out and the relevant damage parameters are extracted from these simulations. The results are used in the lifetime models to correlate experimental and predictive results. Shortcomings of the existing life prediction approaches are discussed and ways to improve lifetime prediction are suggested.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"37 22","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133391665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Direct liquid thermal management of 3D chip stacks","authors":"A. Bar-Cohen, K. Geisler, E. Rahim","doi":"10.1109/EPTC.2009.5416562","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416562","url":null,"abstract":"Chip stacks are a crucial building block in advanced 3D microsystem architectures and can accommodate shorter interconnect distances between devices, reduced power dissipation, and improved electrical performance. Although enhanced conduction can serve to transfer the dissipated heat to the top and sides of the package and/or down to the underlying PCB, effective thermal management of stacked chips remains a most difficult challenge. Immersion cooling techniques, which provide convective and/or ebullient heat transfer, along with buoyant fluid flow, in the narrow gaps separating adjacent chips, are a most promising alternative to conduction cooling of three-dimensional chip stacks. Application of the available theories, correlations, and experimental data are shown to reveal that passive immersion cooling-relying on natural convection and/or pool boiling — could provide the requisite thermal management capability for 3D chip stacks anticipated for use in much of the portable equipment category. Alternatively, pumped flow of dielectric liquids through the microgaps in 3D stacks, providing single phase and/or flow boiling heat absorption, could meet many of the most extreme thermal management requirements for highperformance 3D microsystems. Use of deionized water is shown to provide an order of magnitude improvement in heat dissipation relative to the available dielectric fluids.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"91 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128012464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The effect of leadframe finishing towards package delamination","authors":"L. Fong","doi":"10.1109/EPTC.2009.5416540","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416540","url":null,"abstract":"Package reliability depends on the integrity of the interface between various materials. Key interfaces are between epoxy-based mold compound to leadframe and chip surfaces. In the present work, the adhesion of epoxy-based mold compound and copper leadframe with various finishing is being discussed. It is observed that dendrite like feature on the leadframe finishing is critical to prevent delamination between the molding compound to leadframe.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121438340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of process parameters on pad damage during Au and Cu ball bonding processes","authors":"I. Qin, A. Shah, C. Huynh, M. Meyer, M. Mayer, Y. Zhou","doi":"10.1109/EPTC.2009.5416482","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416482","url":null,"abstract":"Cu wire bonding is one of the hottest trends in electronic packaging due to the cost and the electrical and thermal performance advantages of Cu wire over Au wire. However, there are many challenges to Cu wire bonding, one of which is the increased stress transmitted to the bond pad during ball bonding process. This high stress is not desirable as it leads to pad damage or cratering in the silicon under the pad. Another issue is pad splash where the pad material is squeezed outside the bonded area, which in severe cases can cause Al pad thinning and depletion. This paper compares the pad stress during wire bonding for equivalent Cu and Au process using state of art piezoresistive microsensors integrated at the bonding pad. To study the root cause of the increased stress, ball bonding is performed with Au and Cu wires using the same levels of ultrasound (USG), bonding force (BF), and impact force (IF) on the microsensor test pad while measuring the pad stress signals in real time. The measured pad stress in ultrasonic direction did not show any significant difference between the Au and Cu ball bonding process. This indicates that the cause of increased stress cannot be attributed to material properties such as hardness alone, and that the differences in bondability and bonding parameters required for the Cu process might be more influential. To achieve optimal bonding results, the Cu process requires higher BF and USG. Such higher settings are the main causes of pad damage. To understand the effect of bonding parameters IF, BF, and USG on pad stress, a detailed DOE is conducted with Cu wire. In addition to conventional bonding parameters, the effect of pre-bleed USG (USG level applied during impact portion of the bonding) is investigated. One of the most important findings from the DOE is the reduction of pad damage when higher pre-bleed USG levels are used.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128950133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}