2009 11th Electronics Packaging Technology Conference最新文献

{"title":"Novel bumping material for stacking silicon chips","authors":"Kwang-Seong Choi, Ki-Jun Sung, Byeong-Ok Lim, Hyun-Cheol Bae, Sunghae Jung, J. Moon, Y. Eom","doi":"10.1109/EPTC.2009.5416483","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416483","url":null,"abstract":"Bumping processes like the controlled collapse chip connect new process (C4NP) and the immersion solder bumping process for a fine pitch bumping have the disadvantages of the complicated series of process and the possibility of the reliability problems, respectively. To overcome the weak points of these processes, we developed a novel bumping material based on the rheological behavior of the molten droplets of solder in a resin. The novel resin was designed to have the properties of low viscosity for the rheological behavior of the droplets during the bumping process, the elimination of the oxide layer on the solder powder for the wetting on the pad near the melting point of the solder, and no major weight loss caused by the out-gassing. With this novel material, the bumps array of Sn-58Bi solder were formed, and the applicability of the resin to the Sn-3.0Ag-0.5Cu (SAC305 was, also, identified.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125273142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Research on strength descent of wire bonding in the packing","authors":"Zhang Dezheng, Bao Shengxiang, Ma Lili, Lv Dechun","doi":"10.1109/EPTC.2009.5416519","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416519","url":null,"abstract":"For microelectronics packaging, it connects the substrates with pin wire in the way of wire bonding for separate electronic components packing, and also called wire bonding technology. For a long time, rockii effect is thought as the normal invalid forms. But now the more and more study shows Kiekendall voids are the main factors that influence the bonding intensity. Aiming at the model SOT23 transistor, we analysis the form of Kiekendall voids of wire bonding.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122902007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis of power/ground noise effect on performance degradation of analog-to-digital converter","authors":"Woojin Ahn, J. Shim, Jeonghyeon Cho, Minchul Shin, Kyoungchoul Koo, Joungho Kim","doi":"10.1109/EPTC.2009.5416463","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416463","url":null,"abstract":"This paper presents the analysis of the effect of power/ground noise on analog-to-digital converter (ADC). Power/ground noise is one of the noise sources to degrade ADC performance. Power distribution networks of off-chip and on-chip are modeled to analyze the mount of noise coupling and frequency response. Also, power/ground noise effect on ADC circuit is analyzed by spice simulation. It is analyzed and simulated that how noise coupled on power and ground can degrade designed flash ADC performance.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132606432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Application of the latency insertion method to circuits with blackbox macromodel representation","authors":"J. Schutt-Ainé, D. Klokotov, Patrick Goh, Jilin Tan, F. Al-Hawari, Ping Liu, W. Dai","doi":"10.1109/EPTC.2009.5416569","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416569","url":null,"abstract":"In this work the latency insertion method (LIM) is applied to the treatment of blackbox networks described by their frequency-domain scattering parameters. The method allows the simulation of passive macromodels in the LIM environment. This generalization allows LIM to simulate subnetworks with frequency-dependent parameters describing phenomena such as skin effect and substrate loss. The derivation of the algorithms is presented as well as simulation results to validate the method.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134543248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Application of GR&R for productivity improvement","authors":"S.M. Low, S.Y. Lee, W.K. Yong","doi":"10.1109/EPTC.2009.5416396","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416396","url":null,"abstract":"Testing is a check point in semiconductor manufacturing to ensure quality products are delivered to the customer. As demand and complexity of products increases, advanced equipments are used to perform the test. However, the outcome of the tests does not just depend on availability of advanced equipment, but also depends on the consistency and stability of the measuring system, or commonly called gage. Inconsistency and instability of the gage may result in good units being sorted as bad units and eventually being scrapped leading to production yield loss. As a result the gage performance has become an important issue in testing process. Gage Repeatability and Reproducibility (GR&R) is a statistical model to ensure consistency and stability of the measuring system. By performing GR&R study one could determine the uncertainty present in the gage and help to prevent production losses. This paper reports a study on GR&R on a 416 leads 16 bits micro-controller device to check the consistency and stability of the measuring system used. A total of 150 measurement data was collected and analyzed. Incidentally, the study was made at the time one of the test on the micro-controller suffered a comparatively high yield loss. This GR&R study came just at the right time and the results showed inconsistency in the measuring system. Further detailed analysis finally picked up the root cause of the poor GR&R performance in the measuring system. This indicated that GR&R could be used as a powerful tool to improve productivity even for complex semiconductor products.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114857331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The effect of driving waveforms on droplet formation in a piezoelectric inkjet nozzle","authors":"P. Shin, J. Sung","doi":"10.1109/EPTC.2009.5416559","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416559","url":null,"abstract":"In the present study, double waveforms to drive a piezoelectric inkjet nozzle have been applied to the droplet formation of low viscosity liquid. The effect of the driving voltage and time separation between the pulses was observed. Even though several satellites are produced in the single waveform, the droplet formation could be precisely controlled in the double waveform. The shorter is the time separation, the smaller droplet is formed. The main effect of double waveform is that the second pulse reduces the mass and momentum of the ejected liquid.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117135583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of TSV interposer on the thermal performance of FCBGA package","authors":"Y. Hoe, T. Yue, P. Damaruganath, C. T. Chong, J. Lau, Zhang Xiaowu, K. Vaidyanathan","doi":"10.1109/EPTC.2009.5416445","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416445","url":null,"abstract":"In this paper, the effect of TSV (Through Silicon Via) parameters on the equivalent thermal conductivity of TSV interposer and the effect of the TSV interposer on the thermal performance of the package have been elaborated. The modeling approach using in this paper includes compact modeling for the package and detailed modeling for the TSV interposer. The objective of compact modeling is to study the effect of TSV interposer on thermal performance of the package, while the objective of detailed modeling is to extract the equivalent thermal conductivity of TSV interposer which is used for compact modeling. The proposed package in this study includes a large die with fine pitch, a silicon interposer with TSV, a 1-2-1 buildup substrate and a PCB board. In addition, to evaluate the thermal performance of the proposed package, a similar package without the TSV interposer is also modeled in this study for comparison. The results of detailed modeling show that the equivalent thermal conductivity of TSV interposer can be increased by reducing the pitch and via ratio of TSV, as well as increasing the plating thickness of partial filled TSV and using highly conductive filler material. Furthermore, the results of compact modeling reveal that the proposed TSV interposer improves the thermal performance of the package. The thermal resistance of the package decreases when the interposer size and thickness increase, and the equivalent thermal conductivity of TSV interposer has negligible effect on thermal performance of the package.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115133766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effects of fine size lead-free solder ball on the interfacial reactions and joint reliability","authors":"Y. Park, Yong-min Kwon, J. Moon, Young-woo Lee, Jae-Hong Lee, K. Paik","doi":"10.1109/EPTC.2009.5416528","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416528","url":null,"abstract":"To satisfy the requirements of the newest mobile product, smaller solder ball is needed for electronic packages such as chip scale package (CSP). The purpose of this study was to investigate the effect of solder ball size on the interfacial reaction. In this study, 400, 300, and, 200 μm diameter solder balls of 98.5 wt.% Sn, 1 wt.% Ag, and 0.5 wt.% Cu(SAC105) were formed on the Cu/OSP and electroplated Ni/Au pads at 250°C. In the case of the reaction with Cu/OSP, as solder ball size decreased, the thickness of Cu<inf>6</inf>Sn<inf>5</inf> intermetallic compounds (IMCs) increased and Cu concentrations of solder balls increased. In the case of fine solder ball, Cu dissolution rate into molten solder was faster than large solder ball due to its high pad area/solder volume ratio (A/V ratio). Fast Cu dissolution into molten solder promoted the IMC growth. In the case of the reaction with electroplated Ni/Au, (Cu,Ni)<inf>6</inf>Sn<inf>5</inf> IMCs were only formed in the interface of 400 μm solder ball. Both (Cu,Ni)<inf>6</inf>Sn<inf>5</inf> and (Ni,Cu)<inf>3</inf>Sn<inf>4</inf> IMCs were formed at the interface of 300 μm solder ball. (Ni,Cu)<inf>3</inf>Sn<inf>4</inf> IMCs were only formed at the interface of 200 μm solder ball. The absolute Cu contents of 200 μm solder ball was smaller than 300 and 400 μm solder ball due to its smaller volume. (Ni,Cu)<inf>3</inf>Sn<inf>4</inf> IMCs were formed by the insufficient Cu contents in 200 μm solder ball. The substrate design with smaller A/V ratio and the SAC alloy with higher Cu contents (>0.5 wt.%) were recommended to reduce the IMC growth.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"267 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115310219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Experimental methods in monitoring voids formation during flip chip underfill cure process","authors":"Foong Chee Seng, Tee Swee Xian, W. T. Ling","doi":"10.1109/EPTC.2009.5416487","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416487","url":null,"abstract":"In this paper, we discuss a unique combination of experimental analyses employed to monitor, understand, and ultimately eliminate micro voids formation in the epoxy matrix of flip chip underfill during curing. Present day flip chip packages require the use of underfill epoxies to achieve reliable C4 bumps solder joints on the board level. Many different types of underfill epoxy chemistry have been used to varying degree of success. In the case of a particular Freescale high end communication processor packaged in ceramics flip chip, Moisture Resistant Cyanate Ester (MRCE) underfill was determined to offer the optimal board level reliability. Unfortunately, MRCE based underfill is also prone to micro voids formation during curing process. Micro voids trapped in the underfill matrix deteriorate the overall package and board level reliability. In order to eliminate these micro voids, it is important to understand the void formation mechanisms. Reliable methods are required to detect not only the presence of these micro voids, but also the on-set of the micro voids during cure. In typical experiments, only fully cured samples are examined for voids. In the work presented here, we describe a series of experimental analyses that helped us to detect the on-set of the micro voids formation during curing. With knowledge of the micro voids formation on-set at different stages of the cure, we were able to modify the cure parameters to eliminate these voids. Specifically, we have made use of standard video cameras and mechanical cross sectioning to capture evidence of voids formation at different stages of the cure. Differential Scanning Calorimetry (DSC) was used extensively to study the thermal properties of both epoxy underfill and to simulate the heating processes that these materials undergo at assembly. Thermal Gravimetric Analysis (TGA) was used to confirm the micro voids formation mechanism. Scanning Acoustic Microscopy (SAM) was used to confirm the voids formed and voids distribution in the FC-CBGA package in actual assembly process. To complete the analyses, the visual observations were correlated to the measured physical changes and chemical kinetics of the MRCE epoxy. Putting all these information together, we were able to come up with a robust solution to eliminate the micro voids effectively.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123296858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electrodeposition of Sn-Ag-Cu solder alloy for electronics interconnection","authors":"Y. Qin, Changqing Liu, G. Wilcox, K. Zhao, Changhai Wang","doi":"10.1109/EPTC.2009.5416536","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416536","url":null,"abstract":"A pyrophosphate and iodide based bath was investigated for the electrodeposition of near-eutectic Sn-Ag-Cu alloy, which is one of the promising lead-free solder candidates for electronics interconnection. The bath contained pyrophosphate and iodide as chelating agents. The composition of electrodeposits were measured by wavelength dispersive X-ray Spectroscopy (WDS). Different morphologies of deposited films were analysed using scanning electron microscopy (SEM). X-ray diffraction (XRD) data indicated that Sn, Ag3Sn and Cu6Sn5 were present in the “as-electroplated” film. The proposed bath was capable of fine pitch near-eutectic Sn-Ag-Cu solder bumps as demonstrated on a glass test wafer.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127291645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}