Analysis of power/ground noise effect on performance degradation of analog-to-digital converter

Abstract

This paper presents the analysis of the effect of power/ground noise on analog-to-digital converter (ADC). Power/ground noise is one of the noise sources to degrade ADC performance. Power distribution networks of off-chip and on-chip are modeled to analyze the mount of noise coupling and frequency response. Also, power/ground noise effect on ADC circuit is analyzed by spice simulation. It is analyzed and simulated that how noise coupled on power and ground can degrade designed flash ADC performance.