2009 11th Electronics Packaging Technology Conference最新文献

{"title":"Fracture behavior of 96.5Sn3.0Ag0.5Cu solder joint under mixed-mode tensile and shear loading conditions","authors":"K. E. Tan, J. Pang","doi":"10.1109/EPTC.2009.5416535","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416535","url":null,"abstract":"Solder joints are subjected to a complex combined loading condition of tensile and shear deformation. The fracture behavior of solder joints is different when it is subjected to pure-tensile, pure shear or varying combination of mixed-mode tension and shear loading combinations. The observed failure modes can vary from brittle intermetallic (IMC) layer failure to ductile bulk solder shear failure. Under mixed-mode loading, a complex combination of IMC and solder failure mechanism is observed. In this study, the fracture behavior of solder joint will be investigated to study effect of mode mixity and plastic constraint on the failure mechanism. The fracture failure mode and behavior were observed and discussed under a range of fracture load cases.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124825583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Inductors from wafer-level package process for high performance RF applications","authors":"B. Guruprasad, Yaojian Lin, M. P. Chelvam, S. Yoon, Kai Liu, R. Frye","doi":"10.1109/EPTC.2009.5416417","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416417","url":null,"abstract":"In this paper, inductors embedded in a mold material are characterized. Due to the low-loss property of the mold material, plated Cu inductors show high quality-factor (Q) performance. This performance is also better than those of similar inductors implemented from our IPD process. The mold material is not only used as a supporting substrate, but also served as package substrate, which allows the high-Q inductors to be implemented with other RF chips (CMOS PA for example) in one single package. Design methodology for such packaging environment is discussed.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129985671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"TEM interfacial characteristics of thermosonic gold wire bonding on aluminium metallization","authors":"H. Xu, C. Liu, V. Silberschmidt, Z. Chen, M. Sivakumar","doi":"10.1109/EPTC.2009.5416495","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416495","url":null,"abstract":"A native alumina thin film existing on aluminium and its evolution in thermosonic gold wire bonding were characterized using high resolution transmission electron microscopy (HR TEM). It has been found that the partly fracture of this alumina film by the ultrasonic vibration allows the interdiffusion at the Au/Al interface, such that the intermetallic compounds (IMCs) are formed. The IMCs are identified as Au4Al and AuAl2 with a thickness of approximately 300 nm. With a higher ultrasonic energy, IMCs are formed in more contact areas, resulting in a stronger bond. Based on these experimental results, a mechanism of ultrasonic gold wire bonding is proposed, which helps to understand the correlation among ultrasonic energy, interfacial structure and bonding strength.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132407097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improvement of drop shock and TC reliability for large die Wafer Level Packages in mobile application","authors":"Jun-Kyu Lee, Yun-Mook Park, I. Kang, Yong-min Kwon, K. Paik","doi":"10.1109/EPTC.2009.5416464","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416464","url":null,"abstract":"In this study, board level drop shock and TC reliabilities in terms of solder materials and UBM(Under Bump Metallurgy) structures have been evaluated to suggest optimal structures of WLP(Wafer level Packaging) with the large die, high pin counts for mobile application. Test vehicles of WLP have been designed with 5.6×5.6mm die size, 340 um thickness (including backside protection film), 14×14 ball array, 400 um ball pitch. Firstly, effect of solder ball composition has been investigated through BLR(Board Level Reliability) tests using electroplated Cu UBM with which solder compositions are SAC305, SAC125-0.05Ni, SAC105, Sn0.7Cu respectively. Secondly, effect of UBM structure has been confirmed under SAC305 ball composition, with which UBM structures are Cu UBM, Ni base-UBM, and direct ball attaching without UBM. Additionally, effect of dielectric materials and thickness for the reliability has been investigated. For the condition of BLR tests, drop tests have been performed under JEDEC Condition B (1500G, 0.5millisecond duration, half-sin pulse), as listed JESD22-B110. Resistance variation was observed by in-situ electrical monitoring during drop test. In case of TC test, the condition was −45~125 D, 2cph (cycles per hour), and resistances of daisy chain were measured every 100cycles. Lifetime statistics for WLP with each design and factors have been compared through the Weibull plot for cumulative failure rate after TC and drop shock tests, respectively. Also, the observation of fracture mode through cross-section analysis and FEM simulation for the thermo-mechanical fatigue has been conducted to define the failure mechanism for each reliability test.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131962170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wafer Backside CoatingTM of electrically conductive die attach adhesives for small IC packaging","authors":"Law Wai Ling, E. Erfe, Aldrin Vaquilar, L. Khor, K. C. Thong, Nicole Yong, Ng Peng Nam, T. Winster, Xuan Hong, Jonathan Israel","doi":"10.1109/EPTC.2009.5416451","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416451","url":null,"abstract":"The complexity of electronic devices is increasing rapidly. Mobile phones, camcorders and MP3 players are examples of devices that continue to incorporate more functionality into increasingly smaller footprints. Package designers have been able to accommodate these new requirements in some cases by reducing the outline dimensions of the semiconductor package so that they are only slightly larger than the silicon chip they protect. This design methodology, however, poses challenges for the die attach adhesive. In a traditional die attach process, paste is dispensed onto the leadframe pad and the chip placed into the paste. The leadframe pad must be designed significantly larger than the chip, to allow for the flow of the paste and the formation of a fillet around the die edge. In addition, the die must have a minimum thickness to prevent the paste flowing onto the top surface of the chip. One way to overcome these difficulties is to use a no-flow die attach which does not form a fillet. This allows the size of the leadframe pad to be reduced to a dimension smaller than the chip itself and also enables the use of thinner die. Die attach adhesive supplied as a film is one approach to this, but there are issues with cost and some restrictions on the adhesive thickness that is available. To address these issues, Wafer Backside Coating™ (WBC™) was developed to apply a non-conductive die attach material. Following this, the use of a highly conductive (silver-filled) WBC paste was described to reduce costs in the packaging of discrete devices. This paper describes the use of a novel conductive Wafer Backside Coating (WBCTM) die attach adhesive that delivers good performance and reliability, with negligible fillet size, that can be used over a wide range of die sizes. This work explores the manufacturability of the WBC conductive material, especially in terms of stencil printability, sawing and die attach. Relevant manufacturability responses (such as stencil open time, die shear strength, die tilt, coverage, etc.) are discussed. Finally, data is presented to confirm that functional devices achieve MSL L1/260 and as well as long term reliability testing.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125418233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of thin film dielectric embedded 3D stacked package","authors":"S. W. Ho, N. Su, L. Lim, Siong Chiew Ong, W. Lee, V. S. Rao","doi":"10.1109/EPTC.2009.5416552","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416552","url":null,"abstract":"In this paper, a process for embedding and interconnecting three dimensional (3D) thin chips stacked in multilayer dielectric at wafer level is presented. Chips of different dimensions are thinned to 30 μm thickness using conventional back-grinding and singulated by dicing. Thin chips of different dimensions were then stacked onto a silicon carrier and embedded in multilayer of pre-formed photo-dielectric film using a vacuum lamination process. Photo-lithography process was used to develop the micro-vias in the dielectric film and thin film metallization is used to form interconnection between the vertically stacked chips. Under bump metallization is processed on the fan-out region of the thin film metallization lines for board level connectivity. Finally, the silicon carrier is removed to release the embedded 3D stacked package. The embedded 3D stacked package fabricated has a thickness of 110 μm and electrical measurements shows good electrical connectivity between the 2 chips stacked and the fan-out metallization lines.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123326691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Assembly and reliability of micro-bumped chips with Through-silicon Vias (TSV) interposer","authors":"Y. Y. Ong, T. Chai, Daquan Yu, M.L. Thew, Eipa Myo, L. Wai, M. C. Jong, V. S. Rao, N. Su, Xiaowu Zhang, P. Damaruganath","doi":"10.1109/EPTC.2009.5416505","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416505","url":null,"abstract":"This paper presents the assembly optimization and charcterierization of Through-Silicon Vias (TSV) interposer technology for two 8 × 10mm2 micro-bumped chips. The two micro-bumped chips represent different functional dies in a System-in-package (SiP). In the final test vehicle, one of the micro-bumped chips had 100μm bump pitch and 1,124 I/O; the other micro-bumped chip had 50μm bump pitch and 13,413 I/O. The TSV interposer size is 25 × 25 × 0.3mm3 with CuNiAu as UBM on the top side and SnAgCu bumps on the underside. The conventional substrate size is 45 × 45mm2 with 1-2-1 layer configuration, a ball-grid array (BGA) of 1mm pitch and a core thickness of 0.8mm. The final test vehicle was subjected to MSL3 and TC reliability assessment. The objective of this paper was to incorporate two 8 × 10mm2 micro-bumped chips into TSV interposer. The micro-bumped chips should have no underfill voiding issue and the whole package should be able to pass Moisture Sensitivity Level 3 (MSL3) and Thermal Cycling (TC) reliability assessment. To achieve this objective of incorporating micro-bumped chips into the TSV interposer, the challenges were small standoff height/ low bump pitch of the micro-bumped chip, underfill flowability and its reliability performance. To overcome these challenges, different types of capillary flow underfill, bump layout designs and bump types were evaluated and a quick reliability assessment was used to select the materials and test vehicle parameters for final assembly and reliability assessment.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121610391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Properties of conductive microstructures containing nano sized silver particles","authors":"J. Felba, K. Nitsch, T. Piasecki, S. Tesarski, A. Moscicki, A. Kinart, D. Bonfert, K. Bock","doi":"10.1109/EPTC.2009.5416421","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416421","url":null,"abstract":"The properties of the structures made by ink-jet printing with the use of the ink containing nano silver sized particles are presented. After structures printing on substrate, to obtain good electrical conductivity, sintering process is necessary. It is shown, that thermal process influences strongly the resistance, and after the process the resistivity of printed structures can be only a little bit higher than the value of the bulk material. Also different electrical test proved similarity between printed and bulk silver. It was stated that the adding some polymer materials for mechanical parameters improving of printed materials up to 1.5% of total mass of the ink do not influence significantly electrical parameters of the printed layers.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126470052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling and analysis of coupling between TSVs, metal, and RDL interconnects in TSV-based 3D IC with silicon interposer","authors":"Kihyun Yoon, Gawon Kim, Woojin Lee, Taigon Song, Junho Lee, Hyungdong Lee, Kunwoo Park, Joungho Kim","doi":"10.1109/EPTC.2009.5416458","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416458","url":null,"abstract":"In this paper, we present a lumped element model for coupled interconnect structures of TSV, metal interconnects, and Redistribution Layer (RDL) in Through-Silicon-Via (TSV)-based 3D IC with silicon interposer. We also analyzed the electrical characteristic of coupling between 3D silicon interposer interconnects. The equivalent lumped model is derived and verified with the S-parameter measurement results. The lumped model for TSV, metal, and RDL combined interconnects is verified with the EM solver simulation results. The S-parameter from the proposed model shows good agreement with the result from the measurement and simulation up to 20GHz. We also proposed shielding structures to suppress coupling between silicon interposer interconnects.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115954356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Minimization of tin whisker growth for ultra-low tin whisker applications","authors":"R. Schetty, W. Sepp","doi":"10.1109/EPTC.2009.5416547","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416547","url":null,"abstract":"Establishment of common metrics for testing of lead free electrodeposits used in electronics applications in the form of industry standard JEDEC JESD201 has resulted in common ground for analysis and reporting of tin whisker growth. Successful satisfaction of JESD201's maximum whisker length (MWL) requirements, currently set at MWL = 40 microns for Class II components for both the high temperature/humidity and ambient test conditions and MWL=45 microns for the thermal cycling requirement, is now common. However, some high-reliability end users expect component suppliers to meet MWL requirements beyond that of the JEDEC standard, and it is conceivable that further reduction of JEDEC MWL requirements may ultimately be required; MWL requirements of 30 microns, 20 microns or even less is possible in the future. This paper will discuss several methods for satisfying future ultra-low tin whisker growth requirements. The first method is the development of a new matte tin electroplating chemistry that produces a deposit which exhibits preferred grain morphology. The second method is the development of a new tin-silver alloy electroplating process which deposits ~95% tin / 5% silver alloy. Tin whisker results from these deposits obtained from both laboratory and production environments will be provided, as well as discussions on mechanistic explanations for the reduced tin whisker growth observed using these two methods.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114258559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}