2009 11th Electronics Packaging Technology Conference最新文献

{"title":"Fabrication of fully embedded board-level optical interconnects and optoelectronic printed circuit boards","authors":"C.C. Chang, C.J. Chang, J. Lau, Allison Chang, T. Tang, S. Chiang, Maurice Lee, T. Tseng, T. Wei, L. L. Shiah, Yap Guan Jie, C. Teo, J. Chai","doi":"10.1109/EPTC.2009.5416403","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416403","url":null,"abstract":"The manufacturing processes of an optoelectronic printed circuit board (OEPCB) with an embedded board-level polymeric waveguide and vertical-optical channel interconnection are presented in this paper. The optoelectronic packages contain one vertical cavity surface emitting laser (VCSEL), one photo detector (PD), surface mount technology (SMT) components and one fully embedded board-level optical interconnects. The first step is to fabricate a polymeric waveguide structure with two 45-degree mirrors, and then embedded the waveguide in the center with two prepreg to form a horizontal optical channel inside a printing circuit board by a two-step laminating process. The vertical-optical channel is made by a three-step process, conformal mask forming, laser ablating and copper etching. This vertical channel is connected to the mirror of the horizontal waveguide. A wide, collimated optical beam couples a package board across a narrow, long air gap and provides a large tolerance to misalignment during the SMT process. Key process steps will be discussed and X-ray images will be presented in this paper. Also, characterization measurements of the important electrical and optical parameters are discussed in this paper.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127794285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Intermetallics formation and evolution in pure indium joint for cryogenic application","authors":"X. Cheng, C. Liu, V. Silberschmidt","doi":"10.1109/EPTC.2009.5416484","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416484","url":null,"abstract":"Intermetallic compounds (IMCs) properties play a significant role in determining the reliability of solder joints in service. IMCs and their evolution become more important for devices with micro- or nano-scale joints used in cryogenic applications. In this study, the interfacial reactions of In/Cu and In/Ni/Cu due to low-temperature cycling are investigated. The results illustrate that the character of IMCs is linked to thickness of indium joints exposed to low-temperature cycling. The formation of Cu-In IMCs and Ni-In IMCs are diffusion-controlled, and low-temperature cycling results in brittle IMCs.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122001869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability based design optimization for fine pitch ball grid array: Modeling construction and DOE analysis","authors":"Ke Xue, Jingshen Wu, Haibin Chen, Jingbo Gai, A. Lam","doi":"10.1109/EPTC.2009.5416439","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416439","url":null,"abstract":"This paper presents a reliability based optimization modeling approach demonstrated for the design of fine pitch ball grid array (fpBGA) structure. In this study the focus is on the strategy for handling the uncertainties in the package design inputs and their implementation into the design optimization modeling framework. The analysis of thermo-mechanical behavior of the package is carried out to predict the warpage behavior of the fpBGA package and the die surface stress. A 3D non-linear finite element model including appropriate information of packaging material properties is constructed to predict the thermal-mechanical behavior of fpBGA after molding process. Real samples are fabricated and undergone shadow moiré inspection and analysis to validate the finite element model. A screening experiment based on orthogonal DOE scheme procedure is carried out in order to find out the correlation between the response and input factors (including interactions) and defining their significance. Finally the most essential/significant input factors can be selected to conduct further analysis (response surface reconstruction, interpolation and optimization) with adding more simulation runs.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130201209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Lowest cost of ownership for chip to wafer bonding with the advanced chip to wafer bonding process flow","authors":"A. Sigl, T. Glinsner, C. Pichler, C. Scheiring, P. Kettner","doi":"10.1109/EPTC.2009.5416502","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416502","url":null,"abstract":"The shrinkage and the integration of various functionalities into electrical devices, like computers or mobile phones, lead to an ongoing need for shrinkage of the integrated semiconductor units. One possibility for manufacturing of highly integrated electrical devices is the System in Package (SiP) approach where various semiconductor chips with different functionalities are stacked and electrically connected to each other. The shrinkage affects all levels of the SiP, e.g. the transistor size, the die thickness, the height of the die stack and also the dimension and shape of interconnects between the dies. The shrinkage of the die thickness and the interconnects can cause difficulties of the existing widely used joint technologies, e.g. solder bumping, because of low amount of involved solder, so that the assembly yields drops and the reliability of the interconnects lowers. The Advanced Chip to Wafer (AC2W) bonding is a two step process for stacking and bonding dies on wafers. First all dies are aligned and tacked on the wafer and in the second step all dies are bonded simultaneously permanently to the wafer. This process allows having force while bonding the dies on the wafer. In that way low solder volume interconnects can be formed on a wafer level with high assembly yield and throughput. The Cost of Ownership (CoO) connected with the throughput of the AC2W process can be an order of magnitude smaller then for comparable chip to wafer bonding processes and therefore the AC2W offers a low cost chip to wafer bonding process for high volume production. This paper will show the AC2W bonding process in detail, some issues at die joint shrinkage, a comprehensive throughput and CoO comparison between the AC2W and comparable process flows and the usage of the AC2W for multiple die layer stacking.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134514811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Developments in fine pitch copper wire bonding production","authors":"B. Chylak","doi":"10.1109/EPTC.2009.5416582","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416582","url":null,"abstract":"Copper wire bonding has huge cost advantages over gold wire bonding. Wire bonding and materials companies have invested heavily in R&D in the last 2 or 3 years and are starting to see the fruits of their labor. Low pin count, heavy wire packages have already been converted to copper wire and many companies are in high volume production. An extensive amount of development activity has targeted high pin count (>200 I/O) and high performance applications. Recently this work has paid off, as there has been an increase in this market segment that has drastically exceeded earlier predictions by market analysts. What the recent Research & Development has done is to actually fill in the knowledge gaps for copper wire bonding. This knowledge has fueled technology development, which, in turn, has enabled the current transition to high volume fine pitch production. In this paper I will discuss some of the technology developments that have overcome the challenges and make recommendations for implementing copper wire bonding as a replacement for gold in high volume manufacturing of high pin count packages. Specific areas of technology development that I will cover are advancements in stable free air ball formation, designs and techniques to eliminate or control pad damage, developments in molding compounds, and copper reliability fundamentals.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133895689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Prediction of drop impact reliability of BGA solder joints on FPC","authors":"Jianlin Huang, Q. Chen, Leon Xu, G. Zhang","doi":"10.1109/EPTC.2009.5416466","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416466","url":null,"abstract":"Recently, Flexible Printed Circuit (FPC) is extensively used in portable electronic products because of its excellent flexibility and twistability. Compared with rigid boards, FPC usually experiences much larger deformation in its usages. However, most available packaging-components at the moment are rigid, FPC-contained products may cause failures under accidental mechanical conditions, such as drop, bending and twisting. Many literatures have been published on the reliability of rigid boards, while much less results were reported for the research of drop performance of FPCs [1,2,3]. In this paper, the mechanical reliability of a BGA mounted on FPC under drop impact has been studied by simulations. To make the model more close to the practical products, one plastic cuboid with the size of 89mm×69.5mm×8mm taken as the housing is involved in the simulation model. The FPC mounted with a BGA is fixed in the cuboid through four screw bars and dropped from 1.5 meters height to the concrete ground. Drop direction, BGA layout location and solder joint shape and size, as the three main factors are used in the reliability study. In practical drop reliability tests, six orthogonal drop tests are taken. As well as considered that the simulation sample is rectangle, the simulations of different drop directions are divided into two groups according to if the long housing edge or short housing edge impact with ground firstly. To simulate the different drop impact angle based on the orthogonal drop, several drop cases were built by setting the angle from 0º to 90º between the ground and model. In all of above drop cases, the single difference is the drop direction. To study the impaction of BGA location, simulation cases with the BGA moved from edge to center had been simulated also. The height and the diameter of solder joint is another important factor to the connection reliability. To predict its impaction, solder joint height varied from 0.15mm to 0.23mm and diameter varied from 0.25mm to 0.35mm were considered in the models. Through the corresponding simulations, analysis and comparison, it is found that the strain rate could be up to a peak of 105/s, but most of the time, the strain rate locates in the range of 102/s. The max stress decreases with the increasing of the solder joint height. Drop reliability can be improved by increasing the height of solder joints. The max stress increases when the diameter of the solder joint increased from 0.25mm to 0.3mm, while decreases when the diameter increased from 0.3mm to 0.35mm. Drop reliability can be only improved when the diameter is larger than 0.3mm.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127577400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"3D integration of image sensor SiP using TSV silicon interposer","authors":"M. Wolf, K. Zoschke, A. Klumpp, R. Wieland, M. Klein, L. Nebrich, A. Heinig, I. Limansyah, W. Weber, O. Ehrmann, H. Reichl","doi":"10.1109/EPTC.2009.5416440","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416440","url":null,"abstract":"3D system integration is a fast growing field that encompasses different types of technologies. [1] The technology chosen for a specific application will be selected according to the required electrical performance of the systems, the footprint, cost and time to market. Other important factors are the boundary conditions given for the specific components e.g. die size, integration compatibility, component availability (wafer vs. bare die) and testability. The paper discusses a specific 3D image sensor system for automotive applications. The system is based on wafer level technology using silicon interposer with Through Silicon Vias (TSV´s), a flip chip assembled sensor element and a microcontroller. The specific system concept, the technical solution and results are discussed.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132850531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Semiconductor final test fixture design with microstructure alloy contacts using Finite Element Analysis","authors":"Z. Y. Lam, H. Koay, N. Amin","doi":"10.1109/EPTC.2009.5416435","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416435","url":null,"abstract":"In this paper, a novel electrical contact mechanism that serves as a low insertion-force test socket is investigated by Finite Element Analysis. The proposed electrical contact mechanism is made up of three different materials such as polymer, metallic alloy and liquid metal. Due to the uneven stress distribution of the conventional pogo pin systems, large puncture marks occur on the integrated circuit contacts. The proposed design enhances the overall stress distribution performance of the electrical contact with integrated circuit as found from the analysis. Parameters such as the number of microstructure contacts and the pitch size among them give influential impact on the overall stress distribution performance. Generally, the more the microstructure contact, the more the stress distribution gets evenness. However, the stress distribution becomes saturated when the number of microstructure contacts reaches 16 for a total area of 0.25 mm × 0.25 mm. The pitch size of 0.07 mm gives the best performance for the given total contact area. Any pitch above will set the microstructure contacts to the edges of the contact area, which decreases the stress distribution performance. A factor of safety analysis is performed for the proposed design and a value of 4.9 is achieved, which is almost 5 times greater than the minimum requirement of 1.0.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131908874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Non-destructive electrical measurement of interconnect degradation in early states by the use of RF signals","authors":"M. Kruger, T. Eckert, N. Nissen, H. Reichl","doi":"10.1109/EPTC.2009.5416438","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416438","url":null,"abstract":"This paper presents the electrical measurement of interconnect degradation in micrometer scale. For this approach the changes in a RF measurement signal under artificial interconnect aging conditions are used. Therefore, scattering parameters (S-parameters) are measured and evaluated. This technique overcomes the drawbacks in sensitivity of the more traditional measurement approaches. Test samples consisting of coplanar transmission lines are cut in with a focused ion beam. Cracks in micrometer dimensions are created and measured electrically and non-destructive. In the second part of the paper a measurement method is presented that is able to use a lower signal frequency by getting the same information about the early degradation state. The used method is passive intermodulation distortion measurement (PIM). Finally, both methods are compared to the traditional four-wire-resistance measurement method. The electrical measurement of early degradation states is the first step to a novel generation of reliability monitoring systems.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"2022 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114487705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Understanding materials compatibility issues in electronics packaging","authors":"M. Paulasto-Krockel, T. Laurila, V. Vuorinen","doi":"10.1109/EPTC.2009.5416496","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416496","url":null,"abstract":"This paper presents a method, which helps to understand and control interactions between dissimilar materials in electronics packaging assemblies. The method consisting of thermodynamic and kinetic modeling combined with detailed microstructural analysis is introduced first. The method will then be demonstrated using three examples. First one is taken from an IC metallization level, and explains why and how TaC diffusion barrier reacts with Si. The second example discusses the impact of Cu on the microstructural evolution and degradation of Au-Al bonds. Finally, the third example deals with solder alloy reactions with Ni/Au pad finishes at a circuit board. The results presented explain the redeposition of AuSn4 phase at the pad interface when SnPbAg or SnAg solders are used.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117179098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}