Lowest cost of ownership for chip to wafer bonding with the advanced chip to wafer bonding process flow

Abstract

The shrinkage and the integration of various functionalities into electrical devices, like computers or mobile phones, lead to an ongoing need for shrinkage of the integrated semiconductor units. One possibility for manufacturing of highly integrated electrical devices is the System in Package (SiP) approach where various semiconductor chips with different functionalities are stacked and electrically connected to each other. The shrinkage affects all levels of the SiP, e.g. the transistor size, the die thickness, the height of the die stack and also the dimension and shape of interconnects between the dies. The shrinkage of the die thickness and the interconnects can cause difficulties of the existing widely used joint technologies, e.g. solder bumping, because of low amount of involved solder, so that the assembly yields drops and the reliability of the interconnects lowers. The Advanced Chip to Wafer (AC2W) bonding is a two step process for stacking and bonding dies on wafers. First all dies are aligned and tacked on the wafer and in the second step all dies are bonded simultaneously permanently to the wafer. This process allows having force while bonding the dies on the wafer. In that way low solder volume interconnects can be formed on a wafer level with high assembly yield and throughput. The Cost of Ownership (CoO) connected with the throughput of the AC2W process can be an order of magnitude smaller then for comparable chip to wafer bonding processes and therefore the AC2W offers a low cost chip to wafer bonding process for high volume production. This paper will show the AC2W bonding process in detail, some issues at die joint shrinkage, a comprehensive throughput and CoO comparison between the AC2W and comparable process flows and the usage of the AC2W for multiple die layer stacking.