2020 IEEE International Test Conference (ITC)最新文献_第7页

Advanced Outlier Detection Using Unsupervised Learning for Screening Potential Customer Returns 使用无监督学习筛选潜在客户回报的高级异常值检测

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325225

Hanbin Hu, Nguyen Nguyen, Chen He, Peng Li

引用次数: 10

Selecting Close-to-Functional Path Delay Faults for Test Generation 选择接近功能路径延迟故障进行测试生成

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325255

I. Pomeranz

引用次数: 2

LAIDAR: Learning for Accuracy and Ideal Diagnostic Resolution LAIDAR:准确性和理想诊断分辨率的学习

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325212

Qicheng Huang, Chenlei Fang, R. D. Blanton

引用次数: 1

High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips 基于三维逻辑测试芯片的高缺陷密度良率学习

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325244

Z. Liu, R. D. Blanton

引用次数: 1

Using Volume Cell-aware Diagnosis Results to Improve Physical Failure Analysis Efficiency 利用体积细胞感知诊断结果提高物理故障分析效率

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325262

Hanson Peng, Mao-Yuan Hsia, Man-Ting Pang, I.-Y. Chang, Jeff Fan, Huaxing Tang, Manish Sharma, Wu Yang

{"title":"Using Volume Cell-aware Diagnosis Results to Improve Physical Failure Analysis Efficiency","authors":"Hanson Peng, Mao-Yuan Hsia, Man-Ting Pang, I.-Y. Chang, Jeff Fan, Huaxing Tang, Manish Sharma, Wu Yang","doi":"10.1109/ITC44778.2020.9325262","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325262","url":null,"abstract":"Statistical analysis based on layout-aware scan diagnosis has been successfully used for identifying defect root causes and reducing physical failure analysis (PFA) efforts, especially for interconnect defects. With increasing complexity and density of designs manufactured by FinFET technologies, more and more cell internal defects are observed. For such defects, the root cause deconvolution (RCD) and PFA based on layout-aware diagnosis learning become less efficient because diagnosis reports can only call out cell instances, but can’t pinpoint the defect location within the suspected cell. Cell-aware diagnosis (CAD) uses analog simulation results to accurately locate defects inside standard cells. The cell-aware RCD (RCAD) provides a comprehensive defect pareto for both cell-internal defects and interconnect defects. Both techniques can be very beneficial for PFA. In this work, we present a case study which combines these techniques to successfully identify a systematic cell internal issue caused by a sensitive layout pattern with dramatically improved PFA efficiency for recent silicon data manufactured by an advanced FinFET technology.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116093831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Digital Design Techniques for Dependable High Performance Computing 可靠高性能计算的数字设计技术

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325281

S. Azimi, L. Sterpone

{"title":"Digital Design Techniques for Dependable High Performance Computing","authors":"S. Azimi, L. Sterpone","doi":"10.1109/ITC44778.2020.9325281","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325281","url":null,"abstract":"As today’s process technologies continuously scale down, circuits become increasingly more vulnerable to radiation-induced soft errors in nanoscale VLSI technologies. The reduction of node capacitance and supply voltages coupled with increasingly denser chips are raising soft error rates and making them an important design issue. This research work is focused on the development of design techniques for high-reliability modern VLSI technologies, focusing mainly on Radiation-induced Single Event Transient. In this work, we evaluate the complete life-cycle of the SET pulse from the generation to the mitigation. A new simulation tool, Rad-Ray, has been developed to simulate and model the passage of heavy ion into the silicon matter of modern Integrated Circuit and predict the transient voltage pulse taking into account the physical description of the design. An analysis and mitigation tool has been developed to evaluate the propagation of the predicted SET pulses within the circuit and apply a selective mitigation technique to the sensitive nodes of the circuit. The analysis and mitigation tools have been applied to many industrial projects as well as the EUCLID space mission project, including more than ten modules. The obtained results demonstrated the effectiveness of the proposed tools.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"237 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116296830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

At-speed DfT Architecture for Bundled-data Design 用于捆绑数据设计的高速DfT体系结构

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325261

R. Guazzelli, L. Fesquet

{"title":"At-speed DfT Architecture for Bundled-data Design","authors":"R. Guazzelli, L. Fesquet","doi":"10.1109/ITC44778.2020.9325261","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325261","url":null,"abstract":"At-speed testing for asynchronous circuits is still an open concern in the literature. Due to its timing constraints between control and data paths, Design for Testability (DfT) methodologies must test both control and data paths at the same time in order to guarantee the circuit correctness. As Process Voltage Temperature (PVT) variations significantly impact circuit design in newer CMOS technologies and low-power techniques such as voltage scaling, the timing constraints between control and data paths must be tested after fabrication not only under nominal conditions but through a range of operating conditions. However, this requirement demands modifications in the control and data paths, which are not straightforward and not desirable from a commercial standpoint due to its incompatibility with conventional testing tools. Even with the available testing methodologies for asynchronous circuits in the literature – by adapting the existing techniques for synchronous or creating new ones from scratch – those methodologies usually target the control or data path. This work explores an at-speed testing approach for bundled data circuits, targeting the micropipeline template. The main target of this test approach focuses on whether the sized delay lines in control paths respect the local timing assumptions of the data paths. By adding extra controllability points in the controllers and taking advantage of scan-chain structures, this work targets to generate/stall tokens in controllers, enabling circuit verification through available scan chains.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123789389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Cost-Effective Test Method for screening out Unexpected Failure in High Speed Serial Interface IPs 筛选高速串行接口ip意外故障的经济有效的测试方法

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325235

Sang-Uck Ahn, Beom-Kyu Seo, Hyun-Woo Kim, Yeoun-Sook Shin, Hyung-Tae Kim, Ghil-Geun Oh, Young-Dae Kim

引用次数: 1

BISTLock: Efficient IP Piracy Protection using BIST bstlock:利用BIST进行有效的IP盗版保护

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325210

Siyuan Chen, Jinwook Jung, P. Song, K. Chakrabarty, Gi-Joon Nam

引用次数: 3

Robust DfT Techniques for Built-in Fault Detection in Operational Amplifiers with High Coverage 高覆盖率运算放大器内置故障检测的鲁棒DfT技术

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325226

M. Saikiran, Mona Ganji, Degang Chen

{"title":"Robust DfT Techniques for Built-in Fault Detection in Operational Amplifiers with High Coverage","authors":"M. Saikiran, Mona Ganji, Degang Chen","doi":"10.1109/ITC44778.2020.9325226","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325226","url":null,"abstract":"An operational amplifier (op amp) is a fundamental block used extensively both as a stand-alone device and as a major block embedded in an SoC. To fully characterize an op amp, sophisticated analog and digital testing is required, which is expensive. Fault detection techniques have proved to reduce package cost and test cost by detecting faulty devices early in the test sequence. In this paper, a simple Design for Test (DfT) technique called intentional offset injection is proposed to detect various faults in the op amp. As our proposed method is completely digital, pure digital circuitry can be used, thereby avoiding expensive analog testing. The op amp can be tested with the proposed fault detection method during wafer probe test right after the continuity tests and the faulty devices could be discarded, thereby circumventing time-consuming analog testing. Additionally, our detection scheme can be used for power-on selftest after deployment and for online health monitoring during normal operation. We show that the proposed detection method can provide high fault coverage of 95% with modest area requirements. In this work, we also introduce a detector called digital window comparator which is used to monitor faults in the biasing circuit as well as in the Widlar current reference providing increased fault coverage.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125850201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8