High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips

Abstract

Test vehicles of various types that aim to identify yield detractors are essential for maturing a new semiconductor process before high volume production. Due to large number of unpredictable geometries created by place-and-route, test vehicles that focus on random logic are of the utmost importance. Prior work that utilizes a two-dimensional regular array of logic blocks has demonstrated significant superiority over conventional approaches. In this work, a third dimension is added to ensure efficient diagnosis of multiple defects that frequently occur within a high defect-density environment. Experiments demonstrate a significant improvement in perfect diagnoses over the two-dimensional LCV.