发布求助
文献互助 智能选刊 最新文献

1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers最新文献

筛选
英文 中文
Accurate and efficient evaluation of circuit yield and yield gradients 准确有效地评估电路产率和产率梯度
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129857
P. Feldmann, S. W. Director
{"title":"Accurate and efficient evaluation of circuit yield and yield gradients","authors":"P. Feldmann, S. W. Director","doi":"10.1109/ICCAD.1990.129857","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129857","url":null,"abstract":"A method is described for estimating the yield and yield gradient based on a priori geometric approximation of the acceptability region in the disturbance space. Circuit performance macromodeling is used to construct the acceptability region approximation. While yield evaluation can be carried out in either the performance space or parameter space, it is shown that for monolithic integrated circuits, the gradient of yield can only be estimated accurately in the disturbance space.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114349327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Computing the error escape probability in count-based compaction schemes 计算基于计数的压缩方案中的错误转义概率
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129927
A. Ivanov, Y. Zorian
{"title":"Computing the error escape probability in count-based compaction schemes","authors":"A. Ivanov, Y. Zorian","doi":"10.1109/ICCAD.1990.129927","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129927","url":null,"abstract":"A unified probabilistic model of count-based compaction is presented that relates the probability of occurrence of the 'counted' events to a circuit's fault detection probabilities. This model enables an identical treatment to be made of all the different count-based techniques proposed to date, e.g., ones, transitions, edges, and spectral coefficients. Based on this model, the authors propose a computation technique for determining the error escape associated with these specific, as well as more general, count-based compaction techniques, under various error models.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121834978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Distributed methodology management for design-in-the-large 大规模设计的分布式方法管理
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129921
Wayne Allen, Douglas Rosenthal, K. W. Fiduk
{"title":"Distributed methodology management for design-in-the-large","authors":"Wayne Allen, Douglas Rosenthal, K. W. Fiduk","doi":"10.1109/ICCAD.1990.129921","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129921","url":null,"abstract":"The MCC CAD framework methodology management system (MMS) is used to describe and control distributed engineering activities in terms of a unified design methodology. Methodologies describe the interactions among design tools and design team members necessary to manage the concurrent design activities associated with design-in-the-large (DITL). A distributed process control server (PCS) provides general process control, load balancing, and interprocess communication (IPC) services to effectively support methodology management activities using networked computing resources.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116946381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
MOSP: module selection for pipelined designs with multi-cycle operations MOSP:模块选择与多周期操作的流水线设计
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129883
R. Jain
{"title":"MOSP: module selection for pipelined designs with multi-cycle operations","authors":"R. Jain","doi":"10.1109/ICCAD.1990.129883","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129883","url":null,"abstract":"Selection of appropriate module types from a design library which will be used in the final implementation is called module selection. A solution is presented to the module selection problem for pipelined designs with multicycle operations. The proposed solution technique is based on an area-delay analysis of an RTL design and produces optimal results in milliseconds.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"276 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115296164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
DC parameterized piecewise-function transistor models for bipolar and MOS logic stage delay evaluation 用于双极和MOS逻辑级延迟评估的直流参数化分段函数晶体管模型
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129977
D. Holberg, S. Dutta, L. Pileggi
{"title":"DC parameterized piecewise-function transistor models for bipolar and MOS logic stage delay evaluation","authors":"D. Holberg, S. Dutta, L. Pileggi","doi":"10.1109/ICCAD.1990.129977","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129977","url":null,"abstract":"A novel technique is presented for analyzing nonlinear active devices driving RC trees which accounts for nonlinear behavior in such a way that the accuracy obtained is typically within 10% of SPICE. This is achieved with a tremendous savings in calculation time as compared to SPICE, using exclusively DC parameterized transistor models. These models have been included in a prototype program for analyzing bipolar and CMOS logic-stage delay models. These techniques are currently being extended to provide best-case and worst-case delay approximations in terms of the DC parameterized piecewise-linear and piecewise-quadratic Thevenin models.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124885317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A parallel block-diagonal preconditioned conjugate-gradient solution algorithm for circuit and device simulations 一种用于电路和器件仿真的平行块对角预条件共轭梯度解算法
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129949
K. Mayaram, Ping Yang, J. Chern, R. Burch, L. Arledge, P. Cox
{"title":"A parallel block-diagonal preconditioned conjugate-gradient solution algorithm for circuit and device simulations","authors":"K. Mayaram, Ping Yang, J. Chern, R. Burch, L. Arledge, P. Cox","doi":"10.1109/ICCAD.1990.129949","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129949","url":null,"abstract":"The authors present a general purpose, parallel matrix solver based on the conjugate gradient squared (CGS) method which features a novel preconditioning scheme commensurate with massive parallel computing. The solver algorithm has been successfully used for solving linear systems of equations arising from circuit and device simulations with MOS and bipolar junction transistor (BJT) circuits, both digital and analog, as well as high-level injection conditions in devices. The performance of the algorithm can be further improved by a matrix partitioning scheme.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121058882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
XREF coupling: capacitive coupling error checker 电容耦合错误检查器
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129892
W. Grundmann, Y. Yen
{"title":"XREF coupling: capacitive coupling error checker","authors":"W. Grundmann, Y. Yen","doi":"10.1109/ICCAD.1990.129892","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129892","url":null,"abstract":"Capacitive coupling among critical nodes in a CMOS VLSI circuit can cause disastrous effects on the logical operation of the circuit. At present, the only simulation method that can accurately detect global capacitive coupling errors is the classical circuit simulation, which, due to its limited capacity, is not practical to apply to the entire design. A pattern-independent circuit verification tool, XREF, is presented which can detect and report all possible failures in a design due to capacitive coupling effects.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121573761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Tautology checking using cross-controllability and cross-observability relations 使用交叉可控性和交叉可观察性关系的同义检验
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129833
E. Cerny, C. Mauras
{"title":"Tautology checking using cross-controllability and cross-observability relations","authors":"E. Cerny, C. Mauras","doi":"10.1109/ICCAD.1990.129833","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129833","url":null,"abstract":"A novel method is described for verifying the equivalence between a combinational circuit and its specification, when both are given in a modular (e.g., factored) form. It is based on the notion of cross-controllability and cross-observability relations that exist between the internal logic values across a cut of the joint composition of the circuit and the specification. It is proven that even after abstracting input and other internal variables the relations are sufficient to verify the equivalence. The abstraction allows reduction of the size of the relation, thus permitting the verification of much larger circuits. A report is presented on the verification of an 8*8 parallel multiplier using at most 527 BDD (binary decision diagram) cells of 21 variables. Extensions to sequential circuits are also discussed.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122755522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Automatic high level synthesis of partitioned busses 自动高级合成分区总线
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129909
Christian Ewering
{"title":"Automatic high level synthesis of partitioned busses","authors":"Christian Ewering","doi":"10.1109/ICCAD.1990.129909","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129909","url":null,"abstract":"A high level synthesis system maps operations of the behavior specification to functional units, minimizing the number of registers, multiplexers and wires. Arranging the results by a floorplanner often leads to a rather large amount of space for interconnections. This situation can be drastically improved if partitioned busses are generated instead of individual connections. For this purpose, a parameterized and powerful target architecture is defined. A method is presented which partitions a data flow graph towards a bus oriented design. A novel allocation method is introduced for this purpose. First experiments with this approach were successful and led to very small designs.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124115718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
Exploitation of periodicity in logic simulation of synchronous circuits 周期性在同步电路逻辑仿真中的应用
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129841
R. Razdan, G. Bischoff, E. Ulrich
{"title":"Exploitation of periodicity in logic simulation of synchronous circuits","authors":"R. Razdan, G. Bischoff, E. Ulrich","doi":"10.1109/ICCAD.1990.129841","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129841","url":null,"abstract":"An overwhelming majority of logic designers use synchronous logic design techniques to manage the complexity of their designs and rely on logic simulation techniques for design verification. Yet, logic simulators do not take advantage of the higher abstraction level provided by synchronous logic design techniques to improve their performance. A general technique is presented which takes advantage of the high degree of periodicity common in synchronous logic designs. It is shown that a performance improvement of at least 200% occurs when these techniques are applied within the COSMOS. simulation system to simulate large digital systems.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127081206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信