Automatic high level synthesis of partitioned busses

Abstract

A high level synthesis system maps operations of the behavior specification to functional units, minimizing the number of registers, multiplexers and wires. Arranging the results by a floorplanner often leads to a rather large amount of space for interconnections. This situation can be drastically improved if partitioned busses are generated instead of individual connections. For this purpose, a parameterized and powerful target architecture is defined. A method is presented which partitions a data flow graph towards a bus oriented design. A novel allocation method is introduced for this purpose. First experiments with this approach were successful and led to very small designs.<>