{"title":"A routing system for mixed A/D standard cell LSI's","authors":"I. Harada, H. Kitazawa, T. Kaneko","doi":"10.1109/ICCAD.1990.129930","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129930","url":null,"abstract":"Global and detailed routing algorithms that minimize crosstalk noise between signal lines are described. In mixed analog/digital circuits, crosstalk noise causes chip performance degradation. Thus, the proposed global routing algorithm routes analog nets in the independent area of the digital nets as much as possible. Both the global and detailed routers minimize the number of signal-line crossovers, especially for analog nets, as these crossovers are dominant in crosstalk noise. Double width lines can be used to avoid unexpected voltage drops caused by parasitic resistances. A postprocess automatically puts up shield lines for very noise sensitive wirings to improve the S/N ratio. The experimental results show that the proposed algorithms are effective in reducing the number of crossovers and redundant vias.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134058399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"CADICS-cyclic analog-to-digital converter synthesis","authors":"G. Jusuf, P. Gray, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.1990.129904","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129904","url":null,"abstract":"CADICS is a technology-independent synthesis tool for generating complete netlists and layouts for CMOS cyclic analog-to-digital converters from a set of specifications. The program is capable of synthesizing A/D converters which have a broad range of sampling rate, resolution (up to 12 bits plus sign bit), and silicon area, and performance comparable to a manual approach without using any standard cell libraries. At higher resolutions provisions for internal self-calibration or capacitor trim array are included automatically.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115693768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design for circuit quality: yield maximization, minimax, and Taguchi approach","authors":"M. Styblinski","doi":"10.1109/ICCAD.1990.129855","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129855","url":null,"abstract":"A relationship between yield optimization, deterministic minimax design, and the Taguchi 'on-target' design with variability reduction is established. It is shown that all these and other design approaches can be combined into one coherent methodology, using the same statistical optimization algorithms and the same generic gradient evaluation formulas. A specific choice is controlled by the selection of the generalized membership function w(.) of the acceptability region, and a sequence of the values of the smoothing parameter beta . Moreover, any 'intermediate' approach between the basic types introduced can be defined in a sense similar to the one used in Zadeh's (1968) fuzzy set theory. As a result, circuit quality can be optimized within the same basic methodology, using different design strategies and investigating different trade-offs, e.g., between the performance and yield. Test examples, as well as a practical CMOS circuit are investigated. Convolution smoothing techniques, and the stochastic approximation approach to statistical optimization are utilized.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117278860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Bretschneider, C. Kopf, H. Lagger, A. Hsu, Elizabeth Wei
{"title":"Knowledge based design flow management","authors":"F. Bretschneider, C. Kopf, H. Lagger, A. Hsu, Elizabeth Wei","doi":"10.1109/ICCAD.1990.129922","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129922","url":null,"abstract":"The knowledge regarding design flow management is described and modeled by predicate-transition Petri nets and production rules. The approach offers a clear and flexible tool control mechanism within a CAD framework such that both static and dynamic behavior of a design flow are supported. The authors also demonstrate how different forms of knowledge can be implemented by a rule based system, OPS83, and be integrated in the HILDA CAD framework to guide the users through the design process.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123798733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Finding clusters in VLSI circuits","authors":"J. Garbers, H. Prömel, A. Steger","doi":"10.1109/ICCAD.1990.129970","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129970","url":null,"abstract":"Circuit partitioning plays a fundamental role in hierarchical layout systems. Identifying the strongly connected subcircuits, the clusters, of the logic can significantly reduce the delay of the circuit and the total interconnection length. Finding such a cluster partition however, is NP-complete. The authors propose a fast heuristic algorithm based on a simple, local criterion. They are able to prove that for highly structured circuits the clusters found by this algorithm correspond with high probability to the 'natural' clusters. An application to large scale real world circuits shows that by this method the number of nets cut is reduced by up to 46% compared to the standard mincut approach.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116394987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Malavasi, U. Choudhury, A. Sangiovanni-Vincentelli
{"title":"A routing methodology for analog integrated circuits","authors":"E. Malavasi, U. Choudhury, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.1990.129880","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129880","url":null,"abstract":"A general methodology for the design of the interconnections of analog circuits to meet high-level constraints on performance is described. In this approach, sensitivities of performance to parasitics are computed, and a set of bounding constraints for parasitics is determined. Sensitivities are then used to generate the weights for a cost function-driven analog area router. After the routing is completed, the actual values of critical parasitics are used to check if the user-defined constraints on circuit performance are met. If the requirements have not been satisfied, the bounding constraints generated on the parasitics are used to increase the weights associated with the parasitics which violated the constraints, and the circuit is rerouted. Results validating the effectiveness of this approach for layout-design automation of analog circuits are reported.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122899855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Simulating electromagnetic radiation of printed circuit boards","authors":"H. Heeb, A. Ruehli, J. Janak, S. Daijavad","doi":"10.1109/ICCAD.1990.129934","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129934","url":null,"abstract":"A realistic approach is introduced for the computation of the electromagnetic radiation interference (EMI) from printed circuit boards. The approach is suitable for large problems and real circuit boards can be investigated. Each trace and its source and loads are represented as electrical circuits and a conventional time-domain circuit simulation is used to find the currents. The field is then calculated by applying the free-space Green's function to all currents including the polarization currents. This is, to the authors' knowledge, the first CAD tool which can predict EMI from basic principles.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123502411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new method for assigning signal flow directions to MOS transistors","authors":"Kuen-Jong Lee, Rajiv Gupta, M. Breuer","doi":"10.1109/ICCAD.1990.129962","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129962","url":null,"abstract":"Signal flow directions of MOS transistors have been used in many CAD tools. A graph theoretic approach is presented for determining these directions. A MOS circuit is represented using several undirected graphs called ST-graphs. The direction assignment problem is modeled as a two paths problem in each ST-graph. Necessary and sufficient conditions under which all edges in an ST-graph are unidirectional are derived. A linear time algorithm is presented that assigns directions to all edges in an ST-graph if they all unidirectional. If bidirectional edges exist, the algorithm assigns directions to most edges in the ST-graph, and the remaining edges are resolved by a sequence of additional algorithms. Experimental results validate the performance benefits of this approach.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121555952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Circuit simulation algorithms on a distributed memory multiprocessor system","authors":"J. Trotter, P. Agrawal","doi":"10.1109/ICCAD.1990.129947","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129947","url":null,"abstract":"Shared memory multiprocessors have failed to achieve large speedups because of the processor to memory bottleneck, which gets worse as more processors are used. The authors match a distributed memory architecture to the problem to overcome the processor to memory bottleneck. A study is made of parallel source row and target row directed matrix factorization algorithms where the operations are precompiled at the row level. The authors' contribution is in the formulation and analysis of these factorization algorithms for a distributed memory architecture. The authors evaluate the effectiveness of their approach for processor utilization, memory accesses and communication costs for large matrices corresponding to real VLSI circuits. It is shown quantitatively, using the above metrics, that the source row factorization scheme is the most effective.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121581441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"AWEsim: a program for the efficient analysis of linear(ized) circuits","authors":"X. Huang, V. Raghavan, R. Rohrer","doi":"10.1109/ICCAD.1990.129974","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129974","url":null,"abstract":"Asymptotic waveform evaluation (AWE) is a novel method to analyze linear(ized) circuits. It uses a form of Pade approximation rather than numerical integration to approximate the behavior of linear(ized) circuits in either the time or the frequency domain. Improvements are presented to the theory of AWE to avoid some inherent limitations of Pade approximation. A discussion is presented of the practical aspects that have arisen in the attempt to use AWE in a simulation program called AWEsim. Results are also presented of AWEsim that clearly demonstrate the advantage of AWE over traditional approaches to circuit simulation.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127739070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}