{"title":"cadics -循环模数转换器合成","authors":"G. Jusuf, P. Gray, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.1990.129904","DOIUrl":null,"url":null,"abstract":"CADICS is a technology-independent synthesis tool for generating complete netlists and layouts for CMOS cyclic analog-to-digital converters from a set of specifications. The program is capable of synthesizing A/D converters which have a broad range of sampling rate, resolution (up to 12 bits plus sign bit), and silicon area, and performance comparable to a manual approach without using any standard cell libraries. At higher resolutions provisions for internal self-calibration or capacitor trim array are included automatically.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"103 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"49","resultStr":"{\"title\":\"CADICS-cyclic analog-to-digital converter synthesis\",\"authors\":\"G. Jusuf, P. Gray, A. Sangiovanni-Vincentelli\",\"doi\":\"10.1109/ICCAD.1990.129904\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"CADICS is a technology-independent synthesis tool for generating complete netlists and layouts for CMOS cyclic analog-to-digital converters from a set of specifications. The program is capable of synthesizing A/D converters which have a broad range of sampling rate, resolution (up to 12 bits plus sign bit), and silicon area, and performance comparable to a manual approach without using any standard cell libraries. At higher resolutions provisions for internal self-calibration or capacitor trim array are included automatically.<<ETX>>\",\"PeriodicalId\":242666,\"journal\":{\"name\":\"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers\",\"volume\":\"103 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-11-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"49\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCAD.1990.129904\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCAD.1990.129904","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
CADICS is a technology-independent synthesis tool for generating complete netlists and layouts for CMOS cyclic analog-to-digital converters from a set of specifications. The program is capable of synthesizing A/D converters which have a broad range of sampling rate, resolution (up to 12 bits plus sign bit), and silicon area, and performance comparable to a manual approach without using any standard cell libraries. At higher resolutions provisions for internal self-calibration or capacitor trim array are included automatically.<>