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1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers最新文献

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An O(n/sup 3/logn)-heuristic for microcode bit optimization 微码位优化的O(n/sup 3/logn)启发式算法
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129874
Hong Se-Kyoung, Park In-Cheol, Kyung Chang-Min
{"title":"An O(n/sup 3/logn)-heuristic for microcode bit optimization","authors":"Hong Se-Kyoung, Park In-Cheol, Kyung Chang-Min","doi":"10.1109/ICCAD.1990.129874","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129874","url":null,"abstract":"The authors address the problem of minimizing the control ROM width, which is important in the design of microprogrammed processors, because it directly reduces the silicon area of the control unit. A heuristic algorithm is proposed which is based on graph partitioning. This algorithm results in nearly optimal solutions with the time complexity of O(n/sup 3/log n), where n denotes the number of distinct microoperations. Comparison of the results with earlier works shows that the proposed heuristic performs better in terms of cost and/or CPU time.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130032895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Congestion-driven placement using a new multi-partitioning heuristic 使用新的多分区启发式的拥塞驱动放置
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129917
Stefan Mayrhofer, U. Lauther
{"title":"Congestion-driven placement using a new multi-partitioning heuristic","authors":"Stefan Mayrhofer, U. Lauther","doi":"10.1109/ICCAD.1990.129917","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129917","url":null,"abstract":"A novel hierarchical top down placement technique is presented for circuits implemented in the sea-of-gates design style. It is based on a new hypergraph multi-partitioning algorithm, whose time complexity is linear in the number of pins of a circuit. The partitioning algorithm uses Steiner tress for the modeling of net topologies, which allows taking wiring congestion into account during placement. This leads to a more sophisticated balance criterion compared to conventional min-cut algorithms and consequently to a better distribution of active elements and wiring over the chip area. Experimental results show that the application of the new method makes the wiring of designs considerably easier.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131542906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 66
A new template based approach to module generation 一种新的基于模板的模块生成方法
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129972
J. Conway, G. Beenker
{"title":"A new template based approach to module generation","authors":"J. Conway, G. Beenker","doi":"10.1109/ICCAD.1990.129972","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129972","url":null,"abstract":"A template-based approach to module generation is presented. This approach allows for the fast and efficient design of layout-rule independent, parametrizable layout generators. By virtue of the use of a true hierarchical compactor combined with a powerful module assembly technique, regular layout structures comparable in density to full custom layout can be generated. The procedural part of this approach has been implemented by creating a C++ object-oriented shell around the trapezoidal corner-stitched data structure of the Tailor layout system. A verification technique has also been implemented which guarantees that generated modules are design rule correct when constructed. Results are given for a ROM and an SRAM matrix generator.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133356411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A hierarchical circuit extractor based on new cell overlap analysis 基于新型细胞重叠分析的分层电路提取器
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129891
H. Sawada
{"title":"A hierarchical circuit extractor based on new cell overlap analysis","authors":"H. Sawada","doi":"10.1109/ICCAD.1990.129891","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129891","url":null,"abstract":"An algorithm is presented for cell overlap analysis. With the hierarchical operations set introduced, any type of cell overlap can be mapped into each subcell. The cell abstract is automatically defined without any technology dependent descriptions and the hierarchical structure can be preserved. The algorithm is implemented in a hierarchical circuit extractor called HIPAS. This system can be used for a full chip with more than 200000 transistors.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123603458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
New algorithms for the placement and routing of macro cells 宏细胞放置和路由的新算法
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129918
W. Swartz, C. Sechen
{"title":"New algorithms for the placement and routing of macro cells","authors":"W. Swartz, C. Sechen","doi":"10.1109/ICCAD.1990.129918","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129918","url":null,"abstract":"Novel algorithms are described for timing driven placement and routing of rectilinearly shaped macro cells. Algorithms are also presented for the implementation of simulated annealing, based on a theoretically derived statistical annealing schedule. A negative feedback scheme is described that optimizes the relative weighting between the primary objective term and the penalty function terms in the cost function. A placement refinement method has been developed for rectilinear cells which spaces the cells at a density which avoids the need for post-routing compaction. In addition, a detailed routing method has been developed which avoids the classically difficult problem of defining channels for detailed routing. The result for the ami33 benchmark circuit is better than the previously published results.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"48 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129077919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 109
SNEL: a switch-level simulator using multiple levels of functional abstraction SNEL:使用多层功能抽象的开关级模拟器
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129842
D. Blaauw, Robert B. Mueller-Thuns, D. Saab, P. Banerjee, J. Abraham
{"title":"SNEL: a switch-level simulator using multiple levels of functional abstraction","authors":"D. Blaauw, Robert B. Mueller-Thuns, D. Saab, P. Banerjee, J. Abraham","doi":"10.1109/ICCAD.1990.129842","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129842","url":null,"abstract":"A novel switch-level simulator, called SNEL, is presented. The SNEL simulator preprocesses the circuit description to abstract its functionality prior to simulation. Functional abstraction is concisely defined in terms of the functional domain and the functional application of circuit constructs. SNEL uses four algorithms that operate on levels ranging from single circuit elements to multiple DC-connected components. Since the functional abstraction preserves the complete functionality of the circuit, the accuracy of the simulation is maintained. However, SNEL models the circuit at a higher and more abstract level, which increases its simulation speed. The presented algorithms were implemented and tested on commercial designs. Without functional abstraction, the simulation speed of SNEL is competitive with current simulators. When functional abstraction was used, the simulation speed increased by more than an order of magnitude.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130927632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
QUIETEST: a quiescent current testing methodology for detecting leakage faults 一种检测泄漏故障的静态电流测试方法
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129902
W. Mao, R. K. Gulati, D. K. Goel, M. Ciletti
{"title":"QUIETEST: a quiescent current testing methodology for detecting leakage faults","authors":"W. Mao, R. K. Gulati, D. K. Goel, M. Ciletti","doi":"10.1109/ICCAD.1990.129902","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129902","url":null,"abstract":"A hierarchical leakage fault analysis methodology is proposed for IDDQ (quiescent power supply current) testing of VLSI CMOS circuits. A software system, QUIETEST, has been developed on the basis of this methodology. The software can select a small number of test vectors for IDDQ testing from the provided functional test set. Therefore, the total test time for IDDQ measurements can be reduced significantly to make IDDQ testing of VLSI CMOS circuits feasible in a production test environment. For two VLSI circuits QUIETEST was able to select less than 1% of functional test vectors from the full test set for covering as many leakage faults as would be covered if IDDQ was measured upon the application of 100% of the vectors.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127906653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 124
Rubber band routing and dynamic data representation 橡皮筋路由和动态数据表示
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129838
W. Dai, Raymond Kong, J. Jue
{"title":"Rubber band routing and dynamic data representation","authors":"W. Dai, Raymond Kong, J. Jue","doi":"10.1109/ICCAD.1990.129838","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129838","url":null,"abstract":"A novel methodology and efficient algorithms are presented for performance driven routing based on computational geometry. A dynamic data representation using constrained triangulation is the key to achieving the efficient routability testing and incremental updating of topological routing. Variable width, variable spacing, evenly distributed spacing and thermal via insertion are used to handle crosstalk, switching noise, and thermal resistance problems.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122998486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 65
Computing parametric yield accurately and efficiently 准确、高效地计算参数良率
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129856
L. Milor, A. Sangiovanni-Vincentelli
{"title":"Computing parametric yield accurately and efficiently","authors":"L. Milor, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.1990.129856","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129856","url":null,"abstract":"An algorithm for computing parametric yield is presented. The algorithm uses statistical modeling techniques and takes advantage of incremental knowledge of the problem to reduce significantly the number of simulations needed. Polynomial regression is used to construct simple equations mapping parameters to measurements. These simple polynomial equations can then replace circuit simulations in the Monte Carlo algorithm for computing parametric yield. The algorithm differs from previous statistical modeling algorithms using polynomial regression for three major reasons: first, the random error that is postulated in polynomial regression equations is taken into account when computing parametric yield; second, the variance of the yield is computed; and third, the algorithm is fully automated. Therefore a direct comparison with Monte Carlo methods can be made. Examples indicate that significant speed-ups can be attained over Monte Carlo methods for a large class of problems.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132624368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
Optimal orientations of transistor chains 晶体管链的最佳取向
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129971
T. W. Her, D. F. Wong, T. Freeman
{"title":"Optimal orientations of transistor chains","authors":"T. W. Her, D. F. Wong, T. Freeman","doi":"10.1109/ICCAD.1990.129971","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129971","url":null,"abstract":"A description is given of an O(NL+L log L) time algorithm, where N is the total number of transistor chains and L is the channel length, to determine the orientation of each transistor chain such that the channel density is minimized. It is shown that the problem of flipping chains and subchains to minimize channel density can also be solved optimally. Finally, it is observed that the algorithm can be used to optimally solve a generalized channel routing problem. The algorithm has been implemented in the custom cell synthesis system of the MCC Physical Satellite. For the cells selected from industry, the algorithm reduced channel density by 18%. They also tested the algorithm on several channel routing problems and reductions of up to 30% in channel density were obtained.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131781681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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