发布求助
文献互助 智能选刊 最新文献

1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers最新文献

筛选
英文 中文
Constraint-based channel routing for analog and mixed analog/digital circuits 用于模拟和混合模拟/数字电路的基于约束的通道路由
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129879
U. Choudhury, A. Sangiovanni-Vincentelli
{"title":"Constraint-based channel routing for analog and mixed analog/digital circuits","authors":"U. Choudhury, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.1990.129879","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129879","url":null,"abstract":"A well-defined methodology for mapping the constraints on a set of critical coupling capacitances into constraints in the vertical-constraint (VC) graph of a channel is presented. The approach involves directing undirected edges, adding directed edges and increasing the weights of edges in the VC graph, in order to meet crossover constraints between orthogonal segments and adjacency constraints between parallel segments, while attempting to cause minimum increase in the channel height due to the constraints. A technique to match the parasitics for symmetrical pairs of nets in the channel is also proposed.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134453796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 68
Automatic and semi-automatic verification of switch-level circuits with temporal logic and binary decision diagrams 自动和半自动验证开关级电路与时间逻辑和二进制决策图
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129834
M. Fujita, Y. Matsunaga, Takeo Kakuda
{"title":"Automatic and semi-automatic verification of switch-level circuits with temporal logic and binary decision diagrams","authors":"M. Fujita, Y. Matsunaga, Takeo Kakuda","doi":"10.1109/ICCAD.1990.129834","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129834","url":null,"abstract":"Automatic and semi-automatic verification methods for switch-level circuits are presented. Switch-level circuits with no delay (but with/without charge effects) are automatically verified using a formalism with binary decision diagrams (BDD) and temporal logic. Purely bidirectional transistors, such as those whose signal directions are dynamically determined in operations, are treated in the uniform way as nonbidirectional transistors. In the case of switch-level circuits with arbitrary delays, based on the work by M.E. Leeser (1989), the authors present a semi-automatic verification method which uses a propositional theorem prover using BDD. First some assignments of propositional variables to terms of temporal logic are manually given, and then the automatic theorem prover does verification.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132825620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
On the efficiency of the transition fault model for delay faults 延迟故障的过渡故障模型的有效性
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129900
Manfred Geilert, J. Alt, M. Zimmermann
{"title":"On the efficiency of the transition fault model for delay faults","authors":"Manfred Geilert, J. Alt, M. Zimmermann","doi":"10.1109/ICCAD.1990.129900","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129900","url":null,"abstract":"A study is presented concerning the efficiency of test pattern sets generated with the transition fault model applied to fine grained delay fault models. The authors have developed the delay fault simulator DELFI-a program which is capable of simulating timing failures of combinational circuits using different delay fault models. For the computer experiments the authors selected transition fault test pattern sets because they are very cost-effective to generate. The simulations of benchmark circuits demonstrate that the transition fault test patterns detect gross delay faults even at nodes with redundant stuck-at faults. Furthermore the results show that the transition fault test patterns are not sufficient for small delay faults in the range of a few gate delays. In order to receive a satisfactory coverage for these delay faults, the transition fault test sets must be extended.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132659638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Optimal test set design for analog circuits 模拟电路的最佳测试集设计
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129906
L. Milor, A. Sangiovanni-Vincentelli
{"title":"Optimal test set design for analog circuits","authors":"L. Milor, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.1990.129906","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129906","url":null,"abstract":"Given the high cost of testing analog circuit functionality, it is proposed that tests for analog circuits should be designed to detect faults. An algorithm is presented that reduces functional test sets to only those that are sufficient to find out whether a circuit contains a parametric fault. Examples demonstrate that drastic reductions in test time can be achieved without sacrificing fault coverage.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122441742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 76
High-level delay estimation for technology-independent logic equations 技术无关逻辑方程的高级延迟估计
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129876
D. Wallace, M. Chandrasekhar
{"title":"High-level delay estimation for technology-independent logic equations","authors":"D. Wallace, M. Chandrasekhar","doi":"10.1109/ICCAD.1990.129876","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129876","url":null,"abstract":"A simple model is presented for estimating the delay of a multi-level combinational logic description prior to a technology-dependent mapping phase. The model proposes that delay through a node varies logarithmically with both the complexity and the fanout of the node's logic equation. This is a consequence of the observation that in high performance circuits, both the fan-in and fan-out of cells are bounded by small numbers. Model parameters are derived for three different CMOS ASIC (application specific integrated circuit) libraries, and the authors show how the predicted delays compare with the actual delays for three different industrial designs in each library. This model can serve as a proxy for delay during technology-independent logic optimization, much as literal counts serve as proxies for area.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"264 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115285681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Minimization of symbolic relations 符号关系最小化
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129848
Bill Lin, F. Somenzi
{"title":"Minimization of symbolic relations","authors":"Bill Lin, F. Somenzi","doi":"10.1109/ICCAD.1990.129848","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129848","url":null,"abstract":"The problem of minimizing symbolic relations is addressed. The relevance of this problem in the field of optimal encoding is shown by examples. A binate covering formulation of the optimization problems involved is given, for which several algorithms are available. A novel method is proposed which is based on binary decision diagrams (BDDs) and the authors show how the covering problem can be solved in linear time in that case.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115600119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 75
A single-state-transition fault model for sequential machines 时序机器的单状态转换故障模型
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129887
K. Cheng, Jing-Yang Jou
{"title":"A single-state-transition fault model for sequential machines","authors":"K. Cheng, Jing-Yang Jou","doi":"10.1109/ICCAD.1990.129887","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129887","url":null,"abstract":"A fault model in the state transition level of finite state machines is studied. In this model, called a single-state-transition (SST) fault model, a fault causes a state transition to go to a wrong destination state while leaving its input/output label intact. An analysis is given to show that a test set that detects all SST faults will also detect most multiple-state-transition (MST) faults in practical finite state machines. It is shown that, for an N-state M-transaction machine, the length of the SST fault test set is upper-bounded by 2*M*N/sup 2/ while the length is exponential in terms of N for a checking experiment. Experimental results show that the test set generated for SST faults achieves not only a high single stuck-at fault coverage but also a high transistor fault coverage for a multilevel implementation of the machine.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116754199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Efficient pole zero sensitivity calculation in AWE AWE中高效的极零灵敏度计算
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129975
John Y. Lee, X. Huang, R. Rohrer
{"title":"Efficient pole zero sensitivity calculation in AWE","authors":"John Y. Lee, X. Huang, R. Rohrer","doi":"10.1109/ICCAD.1990.129975","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129975","url":null,"abstract":"Asymptotic waveform evaluation (AWE) is a novel method to approximate the behavior of linear(ized) circuits in either the time or the frequency domain in terms of a dominant pole/zero approximation. An efficient method for calculating the sensitivities of the poles and zeros found by AWE has been developed. Using the adjoint sensitivity method, it is possible to inexpensively compute the sensitivities of the poles and zeros with respect to all circuit parameters, as well as to circuit parasitics. The sensitivities of the poles and zeros show excellent correlation with the perturbation response, and can provide valuable feedback to the circuit designer.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124059735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An integrated hot-carrier degradation simulator for VLSI reliability analysis 用于VLSI可靠性分析的集成热载流子退化模拟器
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129936
Y. Leblebici, S. Kang
{"title":"An integrated hot-carrier degradation simulator for VLSI reliability analysis","authors":"Y. Leblebici, S. Kang","doi":"10.1109/ICCAD.1990.129936","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129936","url":null,"abstract":"A novel integrated simulation tool is presented for estimating the hot-carrier induced degradation of nMOS transistor characteristics and circuit performance. The proposed reliability simulation tool incorporates an accurate one-dimensional MOSFET model for representing the electrical behavior of locally damaged transistors. The hot-carrier induced oxide damage can be specified by only a few parameters, avoiding extensive parameter extractions for the characterization of device damage. The physical degradation model used in the simulation tool includes both of the fundamental device degradation mechanisms, i.e., charge trapping and interface trap generation. A repetitive simulation scheme has been adopted to ensure accurate prediction of the circuit-level degradation process under dynamic operating conditions. The simulation tool provides information on the evolution of device degradation during long-term operation, and on the performance characteristics of the damaged circuit.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124064600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A two-level two-way partitioning algorithm 一种两级双向分区算法
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129969
Yen-Chuen A. Wei, Chung-Kuan Cheng
{"title":"A two-level two-way partitioning algorithm","authors":"Yen-Chuen A. Wei, Chung-Kuan Cheng","doi":"10.1109/ICCAD.1990.129969","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129969","url":null,"abstract":"A two-way partitioning algorithm is presented which significantly improves on the highly unstable results from the traditional Kernighan-Lin based algorithms. The algorithm groups strongly connected components into clusters, and rearranges the clusters into two final subsets with specified sizes. It is known that the grouping operations reduce the complexity and thus improve the results of partitioning very large circuits. However, if the grouping is inappropriate, the partitioning results may degenerate. To prevent degeneration, the authors use a ratio cut approach to do the grouping. By a series of experiments based on the tradeoff between cut capacity and CPU time, the authors determine an optimal value to control the resultant number of groups. Good experimental results have been observed in terms of cut capacity and CPU time.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123955304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信