发布求助
文献互助 智能选刊 最新文献

1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers最新文献

筛选
英文 中文
FOLM-planner: A new floorplanner with a frame overlapping floorplan model suitable for SOG (sea-of-gates) type gate arrays FOLM-planner:一种适用于SOG (sea-of-gates)型栅极阵列的框架重叠平面模型的新型平面规划器
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129863
M. Murofushi, M. Yamada, T. Mitsuhashi
{"title":"FOLM-planner: A new floorplanner with a frame overlapping floorplan model suitable for SOG (sea-of-gates) type gate arrays","authors":"M. Murofushi, M. Yamada, T. Mitsuhashi","doi":"10.1109/ICCAD.1990.129863","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129863","url":null,"abstract":"A floorplanner, FOLM-planner, suitable for SOG gate arrays is presented. FOLM-planner is based on a 'frame overlapping floorplan model, which is free from unnecessary constraints caused by conventional floorplan models, and is easy to use for satisfying timing constraints. FOLM-planner aims at minimizing the net length among frames and controlling frame overlaps for efficient usage of a chip area. To accomplish these objectives, FOLM-planner uses a newly developed force directed method for frame reshaping as well as moving. Experimental results have shown that FOLM layout can shorten the net length inside a frame without the total net length becoming longer.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"106 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124160161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Partitioning of functional models of synchronous digital systems 同步数字系统功能模型的划分
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129884
Rajesh K. Gupta, G. Micheli
{"title":"Partitioning of functional models of synchronous digital systems","authors":"Rajesh K. Gupta, G. Micheli","doi":"10.1109/ICCAD.1990.129884","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129884","url":null,"abstract":"A partitioning technique is presented of functional models that are used in conjunction with high-level synthesis of digital synchronous circuits. The partitioning goal is to synthesize multi-chip systems from one behavioral description that satisfy both chip area constraints and an overall latency timing constraint. There are three major advantages to using partitioning techniques at the functional abstraction level. First, scheduling techniques can be applied concurrently to partitioning. Therefore, partitioning under timing constraints, and in particular under latency constraints, can be performed. Second, the functional model captures large hardware systems with fewer objects (than at the logic netlist abstraction level), making the partitioning algorithm more efficient. Third, hardware sharing tradeoffs can be considered. Hardware partitioning is formulated as a hypergraph partitioning problem. Algorithms for hardware partitioning are presented and experimental results are reported.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128610152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 96
An algebra for switch-level simulation 用于开关级仿真的代数
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129961
I. Hajj
{"title":"An algebra for switch-level simulation","authors":"I. Hajj","doi":"10.1109/ICCAD.1990.129961","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129961","url":null,"abstract":"A methodology is presented for computing the steady-state solution of switch-level networks. The method is based on a matrix algebra similar in many respects to circuit nodal analysis. The formulation steps are similar to the nodal equation formulation steps and the network matrix has the same dimension and structure as the nodal admittance matrix, except that logic operations (min and max operations) are used in formulating and solving the network equations. Solution algorithms are then developed using the new algebra. The approach has been implemented as a part of a mixed-mode simulator which uses partitioning and sparse matrix solution techniques in analyzing a circuit. In its switch-level mode, the simulator can perform logic and concurrent fault simulation using realistic fault models, including bridging faults, and has been found to be competitive with existing switch-level simulators.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129124034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
On the diagnostic resolution of signature analysis 论特征分析的诊断分辨率
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129926
J. Rajski, J. Tyszer, Babak Salimi
{"title":"On the diagnostic resolution of signature analysis","authors":"J. Rajski, J. Tyszer, Babak Salimi","doi":"10.1109/ICCAD.1990.129926","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129926","url":null,"abstract":"An examination was made of the diagnostic properties of signature analysis. By theoretical and experimental studies the authors derived the probabilities that a given number of signatures occur during a test, and that a given number of signatures will be produced uniquely (i.e. by one fault). These characteristics were validated by a series of simulations of the benchmark circuits under test together with a response compaction procedure using linear feedback shift registers (LFSRs) implementing primitive polynomials. The experimental results confirm the validity of the theoretical model. The authors perform further calculations in order to reveal some important relationships between the size of the used LFSR, the total number of faults and the diagnostic resolution of signature analysis. Indeed, these results provide justification for the adoption of a simple formula that encompasses all the factors considered in the signature analysis compaction technique. Because of its simplicity it can be used directly in VLSI BIST design as well as in a wide range of other applications.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129289049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Multi-level logic minimization across latch boundaries 跨锁存器边界的多级逻辑最小化
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129938
Y. Matsunaga, M. Fujita, Takeo Kakuda
{"title":"Multi-level logic minimization across latch boundaries","authors":"Y. Matsunaga, M. Fujita, Takeo Kakuda","doi":"10.1109/ICCAD.1990.129938","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129938","url":null,"abstract":"A method to minimize sequential circuits is presented. It uses permissible functions extended for sequential circuits, and can make use of don't cares derived from network topology. Also, an efficient binary decision diagram (BDD) implementation of the extended permissible functions is presented by introducing edge attributes that indicate time label to the BDD. Circuits including latches can be efficiently minimized with the proposed method.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130669275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
MIS-MV: optimization of multi-level logic with multiple-values inputs MIS-MV:多值输入的多级逻辑优化
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129981
L. Lavagno, S. Malik, R. Brayton, A. Sangiovanni-Vincentelli
{"title":"MIS-MV: optimization of multi-level logic with multiple-values inputs","authors":"L. Lavagno, S. Malik, R. Brayton, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.1990.129981","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129981","url":null,"abstract":"Techniques are presented for the optimization of multi-level logic with multiple-valued input variables. The motivation for this is to tackle the input encoding problem in logic synthesis, where binary codes need to be found for the different values of a symbolic input variable. Multi-level multiple-valued optimization is used to generate constraints that are used to determine the codes. The state assignment problem in sequential logic synthesis can be approximated as an input encoding problem by ignoring the next state field, which is reasonable when the primary output logic, dominates the next state logic. A novel technique is presented for extracting common factors with multiple-valued variables, and it is shown how other multi-level optimization techniques are easily extended with multiple-valued variables. These ideas have been implemented as algorithms in the MIS-MV program. Practical issues are also presented regarding implementation. Experimental results are also given.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130463686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
A new class of Steiner tree heuristics with good performance: the iterated 1-Steiner approach 一类新的具有良好性能的斯坦纳树启发式算法:迭代1-斯坦纳方法
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129944
A. Kahng, G. Robins
{"title":"A new class of Steiner tree heuristics with good performance: the iterated 1-Steiner approach","authors":"A. Kahng, G. Robins","doi":"10.1109/ICCAD.1990.129944","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129944","url":null,"abstract":"Virtually all previous methods for the rectilinear Steiner tree problem begin with a minimum spanning tree topology and rearrange edges to induce Steiner points. This study presents a more direct approach: the authors iteratively find optimal Steiner points to be added to the layout. The method gives improved average-case performance, and also avoids the worst-case examples of existing approaches. Sophisticated computational geometry techniques allow efficient and practical implementation, and the method is naturally suited to real-world VLSI regimes where, e.g., via costs can be high. Extensive performance results show almost 3% wirelength reduction over the best existing methods. A number of variants and extensions are described.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125279241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 61
Touch and cross router 触摸和交叉路由器
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129839
Kaoru Kawamura, Tatsuya Shindo, Toshiyuki Shibuya, Hideki Miwatari, Yoshie Ohki
{"title":"Touch and cross router","authors":"Kaoru Kawamura, Tatsuya Shindo, Toshiyuki Shibuya, Hideki Miwatari, Yoshie Ohki","doi":"10.1109/ICCAD.1990.129839","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129839","url":null,"abstract":"A novel general routing algorithm is presented. Each net is routed to minimize the cost function defined by a weighted sum of penalties. Two types of design rule violations, touches and crosses, are factors of the cost function. Using these violations enables the algorithm to achieve 100% completion even when routing problems have nets which must be considered simultaneously. This type of problem could not be routed completely by conventional rip-up routers. The algorithm was implemented on a newly developed massively parallel computer. Experimental results on Burstein's difficult switch box problem and several small printed circuit boards show that the algorithm is as powerful as a human expert designer.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127058467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Feedback-driven datapath optimization in Fasolt Fasolt中反馈驱动的数据路径优化
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129908
D. Knapp
{"title":"Feedback-driven datapath optimization in Fasolt","authors":"D. Knapp","doi":"10.1109/ICCAD.1990.129908","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129908","url":null,"abstract":"Fasolt is a program that optimizes a register-level datapath design. Fasolt is unique in that it uses layout information to drive the choice of optimizing transformations; hence it is feedback-driven, because it uses low-level information to drive high-level decision making. Fasolt 1.0 uses critical path and channel density to select pairs of wire bundles to be merged, which may necessitate retiming. Hence scheduling and allocation can take wiring into account in a novel way, which has been sufficient to given 10 and 50% area reductions in naive initial designs.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126415953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Evaluation and synthesis of self-monitoring state machines 自监控状态机的评估与综合
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129901
S. H. Robinson, John Paul Shen
{"title":"Evaluation and synthesis of self-monitoring state machines","authors":"S. H. Robinson, John Paul Shen","doi":"10.1109/ICCAD.1990.129901","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129901","url":null,"abstract":"Signature monitoring has proven to be an effective method for concurrent detection of control-flow errors in processors. A recent proposal adapts signature monitoring to the concurrent checking of dedicated controllers or state machines. The authors extend this approach and present theoretical results, including existence-of-solution guarantees, as well as new, efficient synthesis algorithms. The algorithms have been implemented and successfully applied to a variety of machines including all of the machines in the MCNC benchmark set. For most examples, the evaluation and synthesis algorithms exhibit negligible running times and the resulting optimized machines exhibit reasonable overheads. There is strong indication that the efficient synthesis of self-monitoring, and possibly self-testing, state machines is feasible using this approach.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128790694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信