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1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers最新文献

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Algorithms for discrete function manipulation 离散函数操作算法
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129849
A. Srinivasan, T. Kam, S. Malik, R. Brayton
{"title":"Algorithms for discrete function manipulation","authors":"A. Srinivasan, T. Kam, S. Malik, R. Brayton","doi":"10.1109/ICCAD.1990.129849","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129849","url":null,"abstract":"An investigation was made of the analogous graph structure for representing and manipulating discrete variable problems. The authors define the multi-valued decision diagram (MDD), analyze its properties (in particular prove a strong canonical form) and provide algorithms for combining and manipulating MDDs. They give a method for mapping an MDD into an equivalent BDD (binary decision diagram) which allows them to provide a highly efficient implementation using the previously developed BDD packages. A direct implementation of the MDD structure has also been carried out, but this initial implementation has not yet been tuned to the same extent as the BDDs to allow a reasonable comparison to be made. The authors have used the mapping to BDDs to provide an initial understanding of the limits on the sizes of real problems that can be executed. The results are encouraging.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115569295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 310
PHIFACT-a Boolean preprocessor for multi-level logic synthesis 用于多级逻辑合成的布尔预处理器
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129966
F. Crowet, M. Davio, C. Dierieck, J. Durieu, G. Louis, C. Ykman-Couvreur
{"title":"PHIFACT-a Boolean preprocessor for multi-level logic synthesis","authors":"F. Crowet, M. Davio, C. Dierieck, J. Durieu, G. Louis, C. Ykman-Couvreur","doi":"10.1109/ICCAD.1990.129966","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129966","url":null,"abstract":"PHIFACT is a multi-level Boolean optimization program characterized by a controlled time-area trade-off. Its first phase, the Boolean phase, uses Boolean techniques of decomposition and merging to carry out a structural analysis and, in particular, to detect shared circuit parts. Its second phase, the restructuring phase, carries out a systematic exploration of the area-time design space by applying a user controlled sequence of transformations minimizing a parameterized cost function. The obtained results show the feasibility of full Boolean computations and open the way to an important family of new structural analysis techniques.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125339343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Fast overlapped scattered array storage schemes for sparse matrices 稀疏矩阵的快速重叠分散阵列存储方案
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129950
J. Trotter, P. Agrawal
{"title":"Fast overlapped scattered array storage schemes for sparse matrices","authors":"J. Trotter, P. Agrawal","doi":"10.1109/ICCAD.1990.129950","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129950","url":null,"abstract":"Several heuristic schemes for storing large sparse matrices in memory are presented. These heuristics exploit the distribution of the zero and non-zero elements of the matrix rather than just the number of non-zeros. Their performance ranges from very high packing density and acceptable processing time to extremely fast but acceptable packing density. The best packing density is comparable to the Ziegler scheme but at only 20% of the CPU time. The fastest scheme is about two orders of magnitude faster than the Ziegler method but achieves only about 60% of its packing density. Example matrices from circuit simulation data illustrate the superiority of the authors' schemes.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"R-18 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121009591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Floorplanning with pin assignment 楼层规划与别针分配
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129851
M. Pedram, M. Marek-Sadowska, E. Kuh
{"title":"Floorplanning with pin assignment","authors":"M. Pedram, M. Marek-Sadowska, E. Kuh","doi":"10.1109/ICCAD.1990.129851","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129851","url":null,"abstract":"A hierarchical technique is presented for floorplanning and pin assignment of general cell layouts. Given a set of cells with their shape lists, a layout aspect ratio, relative positions of the external I/O pads and upper bound delay constraints for a set of critical nets, the authors determine shapes and positions of the cells, locations of the floating pins on cells and a global routing solution such that a linear combination of the layout area, the total interconnection length and constraint violations for critical nets is minimized. Floorplanning, pin assignment and global routing influence one another during the hierarchical steps of the algorithm. The pin assignment algorithm is flexible and allows various user specified constraints such as pre-specified pin locations, feedthrough pins, length-critical nets and planar net topologies. Placement, timing and floorplanning results for a Xerox general cell benchmark are reported.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127720730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Partial scan by use of empirical testability 部分扫描利用经验可测性
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129912
K. Kim, C. Kime
{"title":"Partial scan by use of empirical testability","authors":"K. Kim, C. Kime","doi":"10.1109/ICCAD.1990.129912","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129912","url":null,"abstract":"The objective of the partial scan method proposed is to obtain maximum fault coverage for the number of scan elements selected. Empirical testability difference (ETD), a measure of the potential improvement in the overall testability of the circuit, is used to successively select storage elements for scan. ETD is calculated by using testability measures based on empirical evaluation of the circuit with the actual test sequence generator. In addition, ETD focuses on the hard-to-detect faults rather than all faults once such faults are known. The method has been extensively tested with ten of the sequential circuits given by F. Brglez et al. (1989) using the FASTEST provided by T. Kelsey and K. Saluja (1989). The results of these tests indicate that ETD yields on average either 27% of the number of uncovered faults for the same number of scan elements or 21% fewer scan elements for the same fault coverage compared to the other methods studied.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"1978 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130208485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
A new global router based on a flow model and linear assignment 一种新的基于流模型和线性分配的全局路由器
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129836
G. Meixner, U. Lauther
{"title":"A new global router based on a flow model and linear assignment","authors":"G. Meixner, U. Lauther","doi":"10.1109/ICCAD.1990.129836","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129836","url":null,"abstract":"A novel heuristic for global routing in graphs is developed. Based on a flow model it can handle many nets simultaneously, thus reducing the net ordering problem. To demonstrate the validity of the method it was applied to standard cell design style. For this application the authors combined the flow model approach with linear assignment to achieve a hierarchical global routing scheme. This procedure is about six times faster than the old flat net by net global router, while producing denser layouts for the majority of testcases. Good quality was achieved in comparison with the TimberwolfSC version 5.4 global router.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128880905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
A unified framework for the formal verification of sequential circuits 一个统一的框架，用于顺序电路的正式验证
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129859
O. Coudert, J. Madre
{"title":"A unified framework for the formal verification of sequential circuits","authors":"O. Coudert, J. Madre","doi":"10.1109/ICCAD.1990.129859","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129859","url":null,"abstract":"A unified framework for the verification of synchronous circuits is presented. Within this framework two verification tasks, verification by actual execution and by simulation, can be automatically performed using algorithms based on the same concepts. The first idea is to manipulate sets of states and sets of transitions instead of individual states and individual transitions. The second idea is to represent these sets by Boolean functions and to replace operations on sets with operations on Boolean functions. A definition is presented of the two problems addressed and then the authors present the verification algorithms. It is shown that these algorithms use the standard set operations in addition to two specific operations called 'Pre' and 'Img'. A brief explanation is presented as to why the basic set operations are very efficiently performed when sets are denoted by the typed decision graphs of their characteristic functions. The Boolean operators 'constrain' and 'restrict', and the function 'expand' that support efficiently the 'Img' and 'Pre' operations are presented. Experimental results are presented and discussed.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131162812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 316
Observability don't care sets and Boolean relations 可观察性不关心集合和布尔关系
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129965
M. Damiani, G. Micheli
{"title":"Observability don't care sets and Boolean relations","authors":"M. Damiani, G. Micheli","doi":"10.1109/ICCAD.1990.129965","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129965","url":null,"abstract":"An algorithm is presented that computes exact or approximate observability don't care (ODC) sets for a multiple-level combinatorial network. The proposed algorithms are efficient because they use only local information. A method for deriving the equivalence classes of a Boolean relation from the ODC sets is then proposed. Experimental results on computing ODC sets are reported.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"2011 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132889485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Logic compilation from graphical dependency notation 从图形依赖符号进行逻辑编译
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129957
J. Lahti, J. Kivelä
{"title":"Logic compilation from graphical dependency notation","authors":"J. Lahti, J. Kivelä","doi":"10.1109/ICCAD.1990.129957","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129957","url":null,"abstract":"A graphical method for digital logic design based on the use of the IEC (International Electrotechnical Commission) dependency notation logic symbol standard as a logic description language is presented. The method combines graphical specification of RTL-level logic functions, schematic capture and logic compilation. A procedure for finding a gate-level realization for the IEC logic symbols is presented. A CAD system called DEMET supporting the design method is also presented. The system can synthesize gate-level netlists from graphical descriptions expressed using the IEC standard. Netlists can be obtained in several widely used formats, including EDIF (Electronic Design Interchange Format) and very high speed integrated circuit hardware description language (VHDL). The system makes it possible to use the IEC logic symbol standard as an intelligent graphical front-end for tools like silicon compilers.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133501929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Extraction of functional information from combinational circuits 组合电路功能信息的提取
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129873
Masahiko Ohmura, H. Yasuura, K. Tamaru
{"title":"Extraction of functional information from combinational circuits","authors":"Masahiko Ohmura, H. Yasuura, K. Tamaru","doi":"10.1109/ICCAD.1990.129873","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129873","url":null,"abstract":"A technique is presented for functional information extraction, which is the transformation of design descriptions from the logic circuit level to the functional level. The authors have developed a functional information extraction system, FINES, which can deal with both logic functions and arithmetic functions. The technique has made use of the characteristics of the functions in order to perform function extraction independent of the circuit structures.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133408537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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