Logic compilation from graphical dependency notation

Abstract

A graphical method for digital logic design based on the use of the IEC (International Electrotechnical Commission) dependency notation logic symbol standard as a logic description language is presented. The method combines graphical specification of RTL-level logic functions, schematic capture and logic compilation. A procedure for finding a gate-level realization for the IEC logic symbols is presented. A CAD system called DEMET supporting the design method is also presented. The system can synthesize gate-level netlists from graphical descriptions expressed using the IEC standard. Netlists can be obtained in several widely used formats, including EDIF (Electronic Design Interchange Format) and very high speed integrated circuit hardware description language (VHDL). The system makes it possible to use the IEC logic symbol standard as an intelligent graphical front-end for tools like silicon compilers.<>