A unified framework for the formal verification of sequential circuits

1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI:10.1109/ICCAD.1990.129859

O. Coudert, J. Madre

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引用次数: 316

Abstract

A unified framework for the verification of synchronous circuits is presented. Within this framework two verification tasks, verification by actual execution and by simulation, can be automatically performed using algorithms based on the same concepts. The first idea is to manipulate sets of states and sets of transitions instead of individual states and individual transitions. The second idea is to represent these sets by Boolean functions and to replace operations on sets with operations on Boolean functions. A definition is presented of the two problems addressed and then the authors present the verification algorithms. It is shown that these algorithms use the standard set operations in addition to two specific operations called 'Pre' and 'Img'. A brief explanation is presented as to why the basic set operations are very efficiently performed when sets are denoted by the typed decision graphs of their characteristic functions. The Boolean operators 'constrain' and 'restrict', and the function 'expand' that support efficiently the 'Img' and 'Pre' operations are presented. Experimental results are presented and discussed.<>

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一个统一的框架，用于顺序电路的正式验证

提出了一种统一的同步电路验证框架。在此框架内，可以使用基于相同概念的算法自动执行两个验证任务，即实际执行验证和模拟验证。第一个想法是操作状态集和转换集，而不是单个状态和单个转换。第二个想法是用布尔函数来表示这些集合并用布尔函数来代替对集合的操作。首先给出了这两个问题的定义，然后给出了验证算法。结果表明，这些算法除了使用“Pre”和“Img”两个特定操作外，还使用了标准集操作。简要解释了当集合由其特征函数的类型化决策图表示时，为什么基本集合操作非常有效地执行。布尔运算符“约束”和“限制”以及函数“扩展”有效地支持“Img”和“Pre”操作。给出了实验结果并进行了讨论。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers

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