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1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers最新文献

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An algorithm for locating logic design errors 一种定位逻辑设计错误的算法
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129955
M. Tomita, Honghai Jiang, Tamotsu Yamamoto, Yoshihiro Hayashi
{"title":"An algorithm for locating logic design errors","authors":"M. Tomita, Honghai Jiang, Tamotsu Yamamoto, Yoshihiro Hayashi","doi":"10.1109/ICCAD.1990.129955","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129955","url":null,"abstract":"Discusses the problem of locating logic design errors, and proposes an algorithm to solve it. Based on the results of logic verification, the authors introduce an input pattern for locating design errors. The pattern contains only one Boolean variable X/X and is used to sensitize the design errors. An algorithm for locating single design errors with the input patterns has been developed. Experimental results have shown the effectiveness of the input patterns and the algorithm for locating single design errors.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114240751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 51
A fast algorithm for performance-driven placement 性能驱动的快速布局算法
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129916
M. Jackson, A. Srinivasan, E. Kuh
{"title":"A fast algorithm for performance-driven placement","authors":"M. Jackson, A. Srinivasan, E. Kuh","doi":"10.1109/ICCAD.1990.129916","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129916","url":null,"abstract":"An algorithm was developed for the placement of small-cell ICs subject to performance constraints that is efficient in terms of speed and memory usage. The approach models wirelength using a nonlinear cost function similar to that of R.S. Tsay et al. (1988) and a timing model which uses a block-oriented representation of paths like that of M.A.B. Jackson and E.S. Kuh (1989). The timing constraints are implicitly represented using a network and nonlinear programming techniques are used to solve the wirelength minimization problem while satisfying the constraints. This allows critical paths to dynamically adjust while the placement changes to minimize wirelength. The solution of the nonlinear programming problem yields an initial placement of cells that may violate slot constraints. The authors propose hierarchical solution techniques to resolve the slot constraints. By exploiting structure inherent in the formulation, a large reduction is achieved in the number of variables that represent the problem. Additionally, developing special techniques to take advantage of the interaction between the timing model and the physical position of the cells enabled the authors to achieve a speed-up of 10-15 times over Jackson and Kuh (1989) even with a crude implementation of the algorithm.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132401651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Efficient automatic diagnosis of digital circuits 高效的数字电路自动诊断
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129954
Liaw Heh-Tyan, Tsaih Jia-Horng, Lin Chen-Shang
{"title":"Efficient automatic diagnosis of digital circuits","authors":"Liaw Heh-Tyan, Tsaih Jia-Horng, Lin Chen-Shang","doi":"10.1109/ICCAD.1990.129954","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129954","url":null,"abstract":"The problem of automatic diagnosis of digital circuits with efficiency is studied. Two improvements over the method of J.C. Madre et al. (1989) are developed to enhance the efficiency of diagnosis. Specifically, the dominance relation in circuit topology is utilized to reduce the search space of possibly correctable gates. In the authors' experiment, the search space is reduced to about one-half. A novel divide-and-conquer technique to determine the correct gate function is proposed.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122054996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
A data flow based architecture for CAD frameworks 基于数据流的CAD框架体系结构
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129959
P. Hamer, M. Treffers
{"title":"A data flow based architecture for CAD frameworks","authors":"P. Hamer, M. Treffers","doi":"10.1109/ICCAD.1990.129959","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129959","url":null,"abstract":"A novel approach to integrating multi-tool design environments is described which involves making a data flow model of the tools and design methodologies within the relevant design environment and storing this model in a database. This information about the design environment is subsequently used as the basis for organizing and accessing the sets of design data which are used and created within this environment. This approach thus provides a bridge between design process related functions (tool invocation, design process checking and auditing, history logging, and design releasing) and functions related to the design data (data identification, data classification, version management, and data browsing). The main advantages of this technique are its user- and system-level simplicity. its ability to handle data in work-in-progress situations, its support for design methodology, its consistent handling of a wide range of data types and flexibility with respect to changes in the design environment.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122236861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Logic simulation and parallel processing 逻辑仿真与并行处理
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129963
V. Agrawal, S. Chakradhar
{"title":"Logic simulation and parallel processing","authors":"V. Agrawal, S. Chakradhar","doi":"10.1109/ICCAD.1990.129963","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129963","url":null,"abstract":"A statistical model is presented of parallel processing based on circuit activity defined as the average number of gates evaluated at a time step. The number of active gates in a processor is assumed to be a random variable with a binomial probability density function. The performance of the multiprocessor system is derived from the maximum order-statistic of these random variables. When the gates can be equally divided among the p processors, the lower bound on speedup is found to be a*p, where a is the average circuit activity. For unequal division of gates, the lower bound on speedup is less than a*p. Interestingly, for very low activity, speedups significantly higher than the lower bounds are possible.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127781076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Performance optimization of pipelined circuits 流水线电路的性能优化
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129939
S. Malik, K. J. Singh, R. Brayton, A. Sangiovanni-Vincentelli
{"title":"Performance optimization of pipelined circuits","authors":"S. Malik, K. J. Singh, R. Brayton, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.1990.129939","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129939","url":null,"abstract":"The problem of minimizing the cycle time of a given pipelined circuit is considered. Existing approaches are sub-optimal since they do not consider the possibility of simultaneously resynthesizing the combinational logic and moving the latches using retiming. In the work of S. Malik et al. (Proc. of the Hawaii Inter. Conf. on System Sciences, 1990) the idea of simultaneous retiming and resynthesis was introduced. The authors use the concepts presented in that work to optimize a pipelined circuit to meet a given cycle time. Given an instance of the pipelined performance optimization problem, an instance of a combinational speedup problem is constructed. A constructive proof is given that the pipelined problem has a solution if and only if the combinational problem has a solution. This result is significant since it shows that it is enough to consider only the combinational speedup problem and all known techniques for that domain can be directly applied to generate a solution for the pipelined problem.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130038949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A usable circuit optimizer for designers 设计人员可用的电路优化器
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129905
D. Hocevar, R. Arora, U. Dasgupta, S. Dasgupta, N. Subramanyam, Sham Kashyap
{"title":"A usable circuit optimizer for designers","authors":"D. Hocevar, R. Arora, U. Dasgupta, S. Dasgupta, N. Subramanyam, Sham Kashyap","doi":"10.1109/ICCAD.1990.129905","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129905","url":null,"abstract":"OASYS, a flexible and efficient system for circuit optimization and performance characterization, is presented. This system has been successful in being accepted in an industrial design environment. A unique aspect of this system is the use of distributed computing resources to reduce the computation time. A structured problem specification methodology was developed which is novel in that it provides the user with much flexibility yet allows simplification through libraries. A user-interface and management system has been built which allows multiple jobs to be run and dynamically monitored and altered. This system has received considerable usage industrially.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117293961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A CAD process scheduling technique 一种CAD工艺调度技术
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129923
T. Miyazaki, T. Hoshino, M. Endo
{"title":"A CAD process scheduling technique","authors":"T. Miyazaki, T. Hoshino, M. Endo","doi":"10.1109/ICCAD.1990.129923","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129923","url":null,"abstract":"Conductor, an integration system for VLSI design tools and their human-interface builder, is described. The main advantage of this system is its unique process control mechanism. Once VLSI designers specify their tasks by using a flow-chart based graphic editor, the system can handle the design process and maintain the design data produced by each tool.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128623769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
GRCA: a global approach for floorplanning synthesis in VLSI macrocell design GRCA: VLSI宏单元设计中平面规划综合的全局方法
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129866
A. Herrigel
{"title":"GRCA: a global approach for floorplanning synthesis in VLSI macrocell design","authors":"A. Herrigel","doi":"10.1109/ICCAD.1990.129866","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129866","url":null,"abstract":"A novel floorplanning method for the macrocell layout style is presented. The floorplan state space is characterized by an equivalence relation to apply efficient solution techniques. A pseudo-polynomial area optimization algorithm is proposed that derives the optimal slicing tree from a given hierarchical floorplan tree. The order of this floorplan tree is at least two and at most five. Extensions of this approach to cover non-slicing floorplans are also described. Since floorplanning and routing are inter-dependent tasks, an improved dynamic updating scheme is proposed to consider interconnect space around each cell during the floorplan assembly. The method has been successfully applied to an industrial design with about 260000 transistors.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131267969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Don't care minimization of multi-level sequential logic networks 不要在意多级顺序逻辑网络的最小化
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129940
Bill Lin, H. Touati, A. Newton
{"title":"Don't care minimization of multi-level sequential logic networks","authors":"Bill Lin, H. Touati, A. Newton","doi":"10.1109/ICCAD.1990.129940","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129940","url":null,"abstract":"The authors address the problem of computing sequential don't cares that arise in the context of multi-level sequential networks and their use in sequential logic synthesis. The key to their approach is the use of binary decision diagram (BDD)-based implicit state space enumeration techniques and multi-level combinational simplification procedures. Using the algorithms described, exact sequential don't care sets for circuits with over 10/sup 68/ states have been successfully computed.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114312248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 81
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