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1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers最新文献

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The component synthesis algorithm: technology mapping for register transfer descriptions 组件合成算法:技术映射用于寄存器转移描述
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129882
Elke A. Rundensteiner, D. Gajski, L. Bic
{"title":"The component synthesis algorithm: technology mapping for register transfer descriptions","authors":"Elke A. Rundensteiner, D. Gajski, L. Bic","doi":"10.1109/ICCAD.1990.129882","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129882","url":null,"abstract":"In functional modeling, one or more micro-architecture components are described as separate concurrent blocks. An algorithm, called the component synthesis algorithm, is presented that automatically synthesizes micro-architecture components for a functional description. Experimental results show that the automated functional synthesis is comparable to the performance of human designers.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"43 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122239979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
An optimal channel pin assignment algorithm 一种最优通道引脚分配算法
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129826
Yang Cai, D. F. Wong
{"title":"An optimal channel pin assignment algorithm","authors":"Yang Cai, D. F. Wong","doi":"10.1109/ICCAD.1990.129826","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129826","url":null,"abstract":"A study is made of the channel pin assignment problem subject to both position and order constraints. The authors show that the problem is NP-hard in general and present a polynomial time optimal algorithm for an important case where the relative orderings of the terminals are completely fixed. They extend their algorithm to solve the problem for the case where there are also separation constraints between some pairs of consecutive terminals optimally in polynomial time. A discussion is presented of how the algorithm can be incorporated into standard cell and building-block layout design systems. Experimental results indicate that by allowing movable terminals, substantial reductions in channel density can be obtained.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120847461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An algorithm for nearly-minimal collapsing of finite-state machine networks 有限状态机网络的近最小崩溃算法
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129846
W. Wolf
{"title":"An algorithm for nearly-minimal collapsing of finite-state machine networks","authors":"W. Wolf","doi":"10.1109/ICCAD.1990.129846","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129846","url":null,"abstract":"An algorithm is presented which simultaneously generates the Cartesian product of a network of finite-state machines and minimizes the resulting product machine. The algorithm can generate collapsed machines, removing a large set of redundant states on the fly, in CPU times comparable to the time required for simple Cartesian product collapsing. The algorithm makes it practical to generate and analyze a much larger class of collapsed FSM networks.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127841235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
On determining scan flip-flops in partial-scan designs 部分扫描设计中扫描触发器的确定
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129914
Dong-Ho Lee, S. Reddy
{"title":"On determining scan flip-flops in partial-scan designs","authors":"Dong-Ho Lee, S. Reddy","doi":"10.1109/ICCAD.1990.129914","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129914","url":null,"abstract":"A report is presented on procedures investigated to determine flip-flops to be scanned in partial-scan designs for sequential circuits. The main idea pursued is to derive a minimal feedback vertex set of the so-called S-graphs. Results of applying optimal and heuristic procedures on a set of benchmark circuits indicate that heuristic methods give fast and near minimal solutions.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114605602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 220
Incorporation of inductors in piecewise approximate circuit simulation 电感在分段近似电路仿真中的应用
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129869
C. Visweswariah, P. Feldmann, R. Rohrer
{"title":"Incorporation of inductors in piecewise approximate circuit simulation","authors":"C. Visweswariah, P. Feldmann, R. Rohrer","doi":"10.1109/ICCAD.1990.129869","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129869","url":null,"abstract":"The incorporation of inductors in a piecewise approximate circuit simulator, enhancing the generality of such a tool, is presented. Most approximate timing simulators preclude inductors from the underlying circuit. Conventional simulators allow inductive effects, but are too inefficient to simulate very large circuits. The formulation presented allows the event-driven simulation of circuits containing inductors, capacitors and general nonlinear elements. The event processing algorithm is based on the conservation of flux and energy. The implementation was tested in a prototype addition to the SPECS simulation environment. In addition, the theory behind the incorporation of mutual inductors is presented. A few benchmarks were run to confirm the veracity of the model. Research into the automatic, dynamic determination of the optimum current resolution would cause the tool to be more efficient, as well as relieve the designer of choosing a current resolution for the inductors in the circuit.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124037335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A hierarchical approach for testing large circuits 一种测试大型电路的分层方法
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129899
Susana Stoica
{"title":"A hierarchical approach for testing large circuits","authors":"Susana Stoica","doi":"10.1109/ICCAD.1990.129899","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129899","url":null,"abstract":"A method and circuit are presented for implementing hierarchical scan. Hierarchical scan (HScan) has two parts: one is a methodology of adding scan type circuits to very large electronic designs in a novel fashion, such that the timing and real estate impact of scan is reduced, and the other is a scan circuit which serves the above methodology. The advantage of HScan is that it can analyze and improve testability on subunits of very large design such that the testability solution remains valid for the full scale design.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133358442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Timing constraints for correct performance 正确性能的时间约束
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129830
H. Youssef, E. Shragowitz
{"title":"Timing constraints for correct performance","authors":"H. Youssef, E. Shragowitz","doi":"10.1109/ICCAD.1990.129830","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129830","url":null,"abstract":"Novel methodology and algorithms for the derivation of timing constraints on all the interconnects were developed and applied to solving layout related timing problems. This methodology is based on detailed information on timing characteristics of cells and nets. A minimax approach for identifying maximal delay bounds for nets which do not violate the timing constraints on any of the logical paths in the design was proposed. An approximation algorithm with proven polynomial time behavior was described. The recursive application of this algorithm results in the distribution of the whole remaining path slacks between the comprising nets, and as a result, zero slack is achieved. The obtained timing bounds were applied to produce layouts free from timing problems.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133258977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
SIMCURRENT-an efficient program for the estimation of the current flow of complex CMOS circuits simcurrent -一个用于估计复杂CMOS电路电流的有效程序
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129935
Ulrich Jagau
{"title":"SIMCURRENT-an efficient program for the estimation of the current flow of complex CMOS circuits","authors":"Ulrich Jagau","doi":"10.1109/ICCAD.1990.129935","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129935","url":null,"abstract":"A novel method for an efficient estimation of the current waveforms of complex CMOS macro cells or modules at the gate level is presented. A prototype computer program-SIMCURRENT-based on this method runs about 5000 times faster than state of the art analog circuit simulators. The accuracy of the current estimation is in the range of about 5%-mean and rms current values-based on simulation results. The investigations are based on actual double layer Al CMOS processes used in industry. The SIMCURRENT program enables the proper layout of power rails which fulfil mean and peak current limits for electromigration. These limits are derived from reliability calculations for the given process. Simulation results for various circuits are presented.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132819751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Exploiting the special structure of conflict and compatibility graphs in high-level synthesis 在高级综合中利用冲突和兼容性图的特殊结构
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129895
D. Springer, D. E. Thomas
{"title":"Exploiting the special structure of conflict and compatibility graphs in high-level synthesis","authors":"D. Springer, D. E. Thomas","doi":"10.1109/ICCAD.1990.129895","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129895","url":null,"abstract":"Two types of graphs are presented: chordal graphs and comparability graphs. Chordal graphs guarantee a minimum number of registers on a larger number of designs. Comparability graphs reduce the complexity and improve clique partitioning algorithms used in high-level synthesis.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116304102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Multi-level logic optimization for large scale ASICs 大规模专用集成电路的多级逻辑优化
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129982
A. Nagoya, Yukihiro Nakamura, K. Oguri, R. Nomura
{"title":"Multi-level logic optimization for large scale ASICs","authors":"A. Nagoya, Yukihiro Nakamura, K. Oguri, R. Nomura","doi":"10.1109/ICCAD.1990.129982","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129982","url":null,"abstract":"The authors developed an efficient high-level synthesis and optimization system for large-scale circuits, which reduces the total number of fan-ins in the technology-independent phase and adjusts speed and area after technology mapping is completed. A description is presented of multi-level logic optimization techniques based on refined weak division methods and additional functions for carrying out good optimization with only a slight overhead. The authors also describe technology mapping and local optimization techniques suitable for high-level CAD systems. The system has shown that multi-level logic optimization in VLSIs with more than 100000 gates (that is, VLSIs whose control logic comprises more than 10000 gate circuits) is possible in practical CPU time.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121024409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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